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ST6369
DATA SHEET
USE IN LIFE SUPPORT DEVICES OR SYSTEMS MUST BE EXPRESSLY AUTHORIZED.
SGS-THOMSON PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF SGS-THOMSON Microelectronics. As used herein :
1. Life support devices or systems are those which (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided with the product, can be reasonably expected to result in significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can reasonably be expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
ST6369 DATASHEET INDEX
Pages
ST6369
.............................................
1 2 4 6 9 15 19 21 22 23 26 29 30 39 40 40 42 43 48 52 53
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ST6369 CORE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MEMORY SPACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WAIT & STOP MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ON-CHIP CLOCK OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INPUT/OUTPUT PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HARDWARE ACTIVATED DIGITAL WATCHDOG FUNCTION . . . . . . . . . . . . . . . . . . . SERIAL PERIPHERAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-BIT PWM D/A CONVERTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-BIT PWM D/A CONVERTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A/D COMPARATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DEDICATED LATCHES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SOFTWARE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ORDERING INFORMATION TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ST63E69 ST63T69
.... .... ..... ............................... ......... .... ..... .. ..... ... ............................ .. ......... ......... .. ...... ...... ... .. .. ....... ........ ......... ........... ..... ...
55 56 58 60 61 67
GENERAL DESCRIPTION . . . . . . . . . . PIN DESCRIPTION . . . . . . . . . . . . . ST63E69,T69 EPROM/OTP DESCRIPTION. ABSOLUTE MAXIMUM RATINGS . . . . . . ORDERING INFORMATION . . . . . . . .
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ST6369
8-BIT HCMOS MCU FOR DIGITAL CONTROLLED MULTI FREQUENCY MONITOR
PRELIMINARY DATA
4.5 to 6V supply operating range 8MHz Maximum Clock Frequency User Program ROM: 7948 Reserved Test ROM: 244 Data ROM: user selectable size Data RAM: 256 Data EEPROM: 384 bytes bytes bytes bytes
40-Pin Dual in Line Plastic Package Up to 23 software programmable general purpose Inputs/Outputs, including 2 direct LED driving Outputs Two Timers each including an 8-bit counter with a 7-bit programmable prescaler Digital Watchdog Function Serial Peripheral Interface (SPI) supporting S-BUS/ I2C BUS and standard serial protocols One 14-Bit PWM D/A Converter Six 6-Bit PWM D/A Converters
ST6369 8K 256 384 7 (Ordering Information at the end of the datasheet)
1
PDIP40
DEVICE SUMMARY
DEVICE ROM (Bytes) RAM EEPROM (Bytes) (Bytes) D/A Conv.
One A/D converter with 0.5V resolution Five interrupt vectors (HSYNC/NMI, Timer 1 & 2, VSYNC, PWR INT.) On-chip clock oscillator ST6369 is supported by pin-to-pin EPROM and OTP versions. The development tool of the ST6369 microcontroller consists of the ST6369-EMU emulation and development system to be connected via a standard RS232 serial line to an MS-DOS Personal Computer.
February 1993
This is Preliminary information from SGS-THOMSON. Details are subject to change without notice.
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ST6369
Figure 1. ST6369 Pin Configuration
DA0 DA1 DA2 DA3 DA4 DA5 PB1 PB2 AD PB4 PB5 PB6 PA0 PA1 PA2 PA3 PA4 PA5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
40 39 38 37 36 35 34 33 32
VDD PC0 ( SCL ) PC1 ( SDA ) PC2 PC3 ( SEN ) PC4 ( PWRIN ) PC5 PC6 ( HSYNC ) PC7 HDA RESET OSCOUT OSCIN TEST VSYNC N.C. N.C. O0 O1 V SS
VR0G1375
ST6369
31 30 29 28 27 26 25 24 23 22 21
GENERAL DESCRIPTION The ST6369 microcontroller is member of the 8-bit HCMOS ST638x family, a series of devices specially oriented to Digital Controlled Multi Frequency Monitor applications. ST6369 members are based on a building block approach: a common core is surrounded by a combination of on-chip peripherals (macrocells) available from a standard library. These peripherals are designed with the same Core technology providing full compatibility and short design time. Many of these macrocells are specially dedicated to DCMF Monitor applications. The macrocells of the ST6369 are: two Timer peripherals each including an 8-bit counter with a 7-bit software programmable prescaler (Timer), a digital hardware activated watchdog function (DHWD), a 14-bit voltage synthesis tuning peripheral, a Serial Peripheral Interface (SPI), six 6-bit PWM D/A converters, an A/D converter with 0.5V resolution, a 14-bit PWM D/A converter. In addition the following memory resources are available: program ROM (8K bytes), data RAM (256 bytes), EEPROM (384 bytes).
PA6 ( HD0 ) 19 PA7 ( HD1 ) 20
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Figure 2. ST6369 Block Diagram
* Refer To Pin Configuration For Additiona l Information TEST
HSYNC/PC6
TEST INTERRUPT Inputs PORT A PORT B PORT C
PA0 PB0
PA7 * PB7 *
VSYNC
USER PROGRAM ROM 8 kBytes
DATA ROM USER SELECTABLE DATA RAM 256 Bytes DATA EEPROM 384 Bytes
SERIAL PERIPHE RAL INTER FACE
PC2,PC4 PC7 * PC0 / SCL PC1 / SDA PC3 / SEN
TIMER 1
TIMER 2
PC
STACK STACK STACK STACK STACK STACK LEVEL LEVEL LEVEL LEVEL LEVEL LEVEL 1 2 3 4 5 6
DIGITAL WATCHDOG/TIMER
D / A Outputs
HDA,DA0 DA5 AD
8-BIT CORE
A/D Input
POWER SUPPLY
OSCILLATOR
RESET
VDD
VSS
OSCin
OSCout
RESET
VR 0B1 753
Table 1. Device Summary
DEVICE ST6369 ROM (Bytes) 8K RAM (Bytes) 256 EEPROM (Bytes) 384 A/D 1 14-bit D/A 1 6-bit D/A 6 EMULATING DEVICES ST63E69, ST63T69
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PIN DESCRIPTION VDD and VSS. Power is supplied to the MCU using these two pins. VDD is power and VSS is the ground connection. OSCIN, OSCOUT. These pins are internally connected to the on-chip oscillator circuit. A quartz crystal or a ceramic resonator can be connected between these two pins in order to allow the correct operation of the MCU with various stability/cost trade-offs. The OSCIN pin is the input pin, the OSCOUT pin is the output pin. RESET. The active low RESET pin is used to start the microcontroller to the beginning of its program. Additionally the quartz crystal oscillator will be disabled when the RESET pin is low to reduce power consumption during reset phase. TEST. The TEST pin must be held at VSS for normal operation. PA0-PA7. These 8 lines are organized as one I/O port (A). Each line may be configured as either an input with or without pull-up resistor or as an output under software control of the data direction register. Pins PA4 to PA7 are configured as open-drain outputs (12V drive). On PA4-PA7 pins the input pull-up option is not available while PA6 and PA7 have additional current driving capability (25mA, VOL:1V). PA0 to PA3 pins are configured as pushpull. PB1-PB2, PB4-PB6. These 5 lines are organized as one I/O port (B). Each line may be configured as either an input with or without internal pull-up resistor or as an output under software control of the data direction register.
PC0-PC7. These 8 lines are organized as one I/O port (C). Each line may be configured as either an input with or without internal pull-up resistor or as an output under software control of the data direction register. Pins PC0 to PC3 are configured as open-drain (5V drive) in output mode while PC4 to PC7 are open-drain with 12V drive and the input pull-up options does not exist on these four pins. PC0, PC1 and PC3 lines when in output mode are "ANDed" with the SPI control signals and are all open-drain. PC0 is connected to the SPI clock signal (SCL), PC1 with the SPI data signal (SDA) while PC3 is connected with SPI enable signal (SEN, used in S-BUS protocol). Pin PC4 and PC6 can also be inputs to software programmable edge sensitive latches which can generate interrupts; PC4 can be connected to Power Interrupt while PC6 can be connected to the HSYNC/NMI interrupt line. DA0-DA5. These pins are the six PWM D/A outputs of the 6-bit on-chip D/A converters. These lines have open-drain outputs with 12V drive. The output repetition rate is 31.25KHz (with 8MHz clock). AD. This is the input of the on-chip 10 levels comparator that can be used to implement the Analog Keyboard function. This pin is an high impedance input able to withstand signals with a peak amplitude up to 12V. VSYNC. This is the Vertical Synchronization pin. This pin is connected to an internal timer interrupt. O0, O1. These two lines are output open-drain pins with 12V drive. HDA. This is the output pin of the on-chip 14-bit PWM D/A Converter. This line is a push-pull output with standard drive.
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Table 2. Pin Summary
Pin Function DA0 to DA5 AD HDA VSYNC TEST OSCIN OSCOUT RESET PA0-PA3 PA4-PA5 PA6-PA7 PB1-PB2 PB4-PB6 PC0-PC3 PC4-PC7 O0, O1 VDD, VSS Description Output, Open-Drain, 12V Input, High Impedance, 12V Output, Push-Pull Input, Pull-up, Schmitt Trigger Input, Pull-Down Input, Resistive Bias, Schmitt Trigger to Reset Logic Only Output, Push-Pull Input, Pull-up, Schmitt Trigger Input I/O, Push-Pull, Software Input Pull-up, Schmitt Trigger Input I/O, Open-Drain, 12V, No Input Pull-up, Schmitt Trigger Input I/O, Open-Drain, 12V, No Input Pull-up, Schmitt Trigger Input, High Drive I/O, Push-Pull, Software Input Pull-up, Schmitt Trigger Input I/O, Push-Pull, Software Input Pull-up, Schmitt Trigger Input I/O, Open-Drain, 5V , Software Input Pull-up, Schmitt Trigger Input I/O, Open-Drain, 12V, No Input Pull-up, Schmitt Trigger Input Output, Open-Drain, 12V Power Supply Pins
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ST6369 CORE The Core of the ST6369 is implemented independently from the I/O or memory configuration. Consequently, it can be treated as an independent centralprocessor communicating with I/O and memory via internal addresses, data, and control busses. The in-core communication is arranged as shown in the following block diagram figure; the controller being externally linked to both the reset and the oscillator, while the core is linked to the dedicated onchip macrocells peripherals via the serial data bus and indirectly for interrupt purposes through the control registers. Registers The ST6369 Core has five registers and three pairs of flags available to the programmer. They are shown in Figure 4 and are explained in the following paragraphs together with the program and data memory page registers. Accumulator (A). The accumulator is an 8-bit general purpose register used in all arithmetic calculations, logical operations, and data manipulations. The accumulator is addressed in the data space as RAM location at the FFH address. Accordingly, the ST6369 instruction set can use the accumulator as any other register of the data space.
Figure 4. Core Programming Model
INDEX REGISTER
b7 b7 b7 b7 b7
X REG. POINTER Y REG. POINTER
V REGISTER W REGISTER
b0
SHORT DIRECT ADDRESSING MODE b0
b0
b0 b0 b0
ACCUMULATOR
b11
PROGRAM COUNTER
SIX LEVELS STACK REGISTER
NORMAL FLAGS INTERRUPT FLAGS NMI FLAGS
C C C
Z Z Z
VA000423
Figure 3. Core Block Diagram
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ST6369 CORE (Continued) Indirect Registers (X, Y). These two indirect registers are used as pointers to the memory locations in the data space. They are used in the register-indirect addressing mode.These registers can be addressed in the data space as RAM locations at the 80H (X) and 81H (Y) addresses. They can also be accessed with the direct, short direct, or bit direct addressing modes. Accordingly, the ST638x instruction set can use the indirect registers as any other register of the data space. Short Direct Registers (V, W). These two registers are used to save one byte in short direct addressing mode. These registers can be addressed in the data space as RAM locations at the 82H (V) and 83H (W) addresses. They can also be accessed with the direct and bit direct addressing modes. Accordingly, the ST638x instruction set can use the short direct registers as any other register of the data space. Program Counter (PC) The program counter is a 12-bit register that contains the address of the next ROM location to be processed by the core. This ROM location may be an opcode, an operand, or an address of operand. The 12-bit length allows the direct addressing of 4096 bytes in the program space. Nevertheless, if the program space contains more than 4096 locations, the further program space can be addressed by using the Program ROM Page Register. The PC value is incremented, after it is read for the address of the current instruction, by sending it through the ALU, so giving the address of the next byte in the program. To execute relative jumps the PC and the offset values are shifted through the ALU, where they will be added, and the result is shifted back into the PC. The program counter can be changed in the following ways: JP (Jump) instruction.... PC= Jump address CALL instruction ........... PC=Call address Relative Branch instructions ................... PC=PC+offset Interrupt........................ PC=Interrupt vector Reset............................ PC=Reset vector RET & RETI instructions............PC=Pop (stack) Normal instruction ........ PC= PC+1 Flags (C, Z) The ST6369 Core includes three pairs of flags that correspond to 3 different modes: normal mode, interrupt mode and Non-Maskable-Interrupt-Mode. Each pair consists of a CARRY flag and a ZERO flag. One pair (CN, ZN) is used during normal operation, one pair is used during the interrupt mode (CI,ZI) and one is used during the not-maskable interrupt mode (CNMI, ZNMI). The ST6369 Core uses the pair of flags that corresponds to the actual mode: as soon as an interrupt (resp. a Non-Maskable-Interrupt) is generated, the ST6369 Core uses the interrupt flags (resp. the NMI flags) instead of the normal flags. When the RETI instruction is executed, the normal flags (resp. the interrupt flags) are restored if the MCU was in the normal mode (resp. in the interrupt mode) before the interrupt. Should be observed that each flag set can only be addressed in its own routine (Not-maskable interrupt, normal interrupt or main routine). The interrupt flags are not cleared during the context switching and so, they remain in the state they were at the exit of the last routine switching. The Carry flag is set when a carry or a borrow occurs during arithmetic operations, otherwise it is cleared. The Carry flag is also set to the value of the bit tested in a bit test instruction, and participates in the rotate left instruction. The Zero flag is set if the result of the last arithmetic or logical operation was equal to zero, otherwise it is cleared. The switching between these three sets is automatically performed when an NMI, an interrupt and a RETI instructions occur. As the NMI mode is automatically selected after the reset of the MCU, the ST6369 Core uses at first the NMI flags. Figure 5. Stack Operation
PROGRAM COUNTER
STACK LEVEL 1 WHEN RET OR RETI OCCURS STACK LEVEL 2 STACK LEVEL 3 STACK LEVEL 4 STACK LEVEL 5 STACK LEVEL 6
WHEN CALL OR INTERRUPT REQUEST OCCURS
VA000424
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ST6369 CORE (Continued) Stack The ST6369 Core includes true LIFO hardware stack that eliminates the need for a stack pointer. The stack consists of six separate 12-bit RAM locations that do not belong to the data space RAM area. When a subroutine call (or interrupt request) occurs, the contents of each level is shifted into the next level while the content of the PC is shifted into the first level (the value of the sixth level will be lost). When subroutine or interrupt return occurs (RET or RETI instructions), the first level register is shifted back into the PC and the value of each level is shifted back into the previous level. These two operating modes are described in Figure 5. Since the accumulator, as all other data space registers, is not stored in this stack the handling of this registers shall be performed inside the subroutine. The stack pointer will remain in its deepest position, if more than 6 calls or interrupts are executed, so that the last return address will be lost. It will also remain in its highest position if the stack is empty and a RET or RETI is executed. In this case the next instruction will be executed. Memory Registers The PRPR can be addressed like a RAM location in the Data Space at the CAH address; nevertheless it is a write-only register that can not be accessed with single-bit operations. This register is used to select the 2-Kbyte ROM bank of the Program Space that will be addressed. The number of the page has to be loaded in the PRPR. The PRPR is not cleared during the MCU initialization and should therefore be defined before jumping out of the static page. Refer to the Program Space description for additional information concerning the use of this register. The PRPR is not modified when an interrupt or a subroutine occurs. Figure 6. Program ROM Page Register
PRPR Program ROM Page Register (CAH, Write Only)
The DRBR can be addressed like a RAM location in the Data Space at the E8H address, nevertheless it is write-only register that can not be accessed with single-bit operations. This register is used to select the desired 64-byte RAM/EEPROM bank of the Data Space. The number of the bank has to be loaded in the DRBR and the instruction has to point to the selected location as it was in the 0 bank (from 00H address to 3FH address). This register is undefined after Reset. Refer to the Data Space description for additional information. The DRBR register is not modified when a interrupt or a subroutine occurs. Figure 7. Data RAM Bank Register
DRBR Data RAM Bank Register (E8H, Write Only) D7 D6 D5 D4 D3 D2 D1 D0
The DRWR register can be addressedlike a RAM location in the Data Space at the C9H address, nevertheless it is write-only register that can not be accessed with single-bit operations. This register is used to move up and down the 64-byte read-only data window (from the 40H address to 7FH address of the Data Space) along the ROM of the MCU by step of 64 bytes. The effective address of the byte to be read as a data in the ROM is obtainedby the concatenationof the 6 less significant bits of the address given in the instruction (as less significant bits) and the content of the DRWR (as most significant bits). Refer to the Data Space description for additional information. Figure 8. Data ROM Window Register
DRWR
D7 D6 D5 D4 D3 D2 D1 D0
Data ROM Window Register (C9H, Write Only) D7 D6 D5 D4 D3 D2 D1 D0
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MEMORY SPACES The MCUs operate in three different memory spaces: Stack Space, Program Space and Data Space. A description of these spaces is shown in Figure 9. Stack Space The stack space consists of six 12 bit registers that are used for stacking subroutine and interrupt return addressesplus the current programcounterregister. Program Space The program space is physically implemented in the ROM and includes all the instructions that are to be executed, as well as the data required for the immediate addressing mode instructions, the reserved test area and user vectors. It is addressed thanks to the 12-bit Program Counter register (PC register) and so, the ST6369 Core can directly address up to 4K bytes of Program Space. Nevertheless, the Program Space can be extended by the addition of 2-Kbyte ROM banks as it is shown in Figure 11 in which a 8K bytes memory is described. These banks are addressed by pointing to the 000H-7FFH locations of the Program Space thanks to the Program Counter, and by writing the appropriate code in the Program ROM Page Register (PRPR) located at the CAH address of the Data Space. Because interrupts and common subFigure 9. Memory Addressing Description Diagram
STACK SPACE
routines should be available all the time only the lower 2K byte of the 4K program space are bank switched while the upper 2K byte can be seen as static space. Table 3 gives the different codes that allows the selection of the corresponding banks. Note that, from the memory point of view, the Page 1 and the Static Page represent the same physical memory: it is only a different way of addressing the same location. Figure 10. 8K Bytes Program Space Addressing Description
Program counter space 0FFFH Static Page Page 1 0800H 07FFH Page 0 0000H Page 1 Static Page Page 2 Page 3 0000H 1FFFH
PROGRAM SPACE
DATA SPACE
00 00h
PROGRAM COUNTER
000h
R AM / EEPR OM BAN KIN G AR EA
0-63
STACK LEVE L 1 STACK LEVE L 2 STACK LEVE L 3 STACK LEVE L 4 STACK LEVE L 5 STACK LEVE L 6
ROM
03Fh 040h
D ATA ROM W IN D OW
07FFh 08 00h
070h 080h 081h 082h 083h 084h
X R EGISTER Y R EGISTER V R EGISTER W R EGIST ER RA M
ROM
0C0h
DA TA R OM W IND OW SELE CT
0FF0h 0FFFh
IN TER R U PT & R ESET VEC TOR S
D ATA R AM BA N K S EL EC T
0FFh
AC C UMU L ATOR
VR001568
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MEMORY SPACES (Continued) Figure 11. Program ROM Page Register
PRPR Program ROM Page Register (CAH, Write Only) D7 D6 D5 D4 D3 D2 D1 D0
PRPR0 PRPR1 UNUSED UNUSED UNUSED
D7-D2. These bits are not used but have to be written to "0". PRPR1-PRPR0. These are the program ROM banking bits and the value loaded selects the corresponding page to be addressed in the lower part of 4K program address space as specified in Table 3. This register is undefined on reset. Table 3. Program ROM Page Register Coding
PRPR1 X 0 0 1 1 PRPR0 X 0 1 0 1 PC11 1 0 0 0 0 Memory Page Static Page (Page 1) Page 0 Page 1 (Static Page) Page 2 Page 3
Note. Only the lower part of address space has been bankswitched because interrupt vectors and common subroutines should be available all the time. The reason of this structure is due to the fact that it is not possible to jump from a dynamic page to another, unless jumping back to the static page, changing contents of PRPR, and, then, jumping to a different dynamic page. Care is required when handling the PRPR as it is write only. For this reason, it is not allowed to change the PRPR contents while executing interrupts drivers, as the driver cannot save and than restore its previous content. Anyway, this operation may be necessary if the sum of common routines and interrupt drivers will take more than 2K bytes; in this case could be necessary to divide the interrupt driver in a (minor) part in the static page (start and end), and in the second (major) part in one dynamic page. If it is impossible to avoid the writing of this register in interrupts drivers, an image of this register must be saved in a RAM location, and each time the program writes the PRPR it writes also the image register. The image register must be written first, so if an interrupt occurs between the two instructions the PRPR is not affected.
Table 4. ST6369 Program ROM Map
ROM Page PAGE 0 Device Address 0000H-007FH 0080H-07FFH 0800H-0F9FH 0FA0H-0FEFH 0FF0H-0FF7H 0FF8H-0FFBH 0FFCH-0FFDH 0FFEH-0FFFH 0000H-000FH 0010H-07FFH 0000H-000FH 0010H-07FFH Description Reserved User ROM User ROM Reserved Interrupt Vectors Reserved NMI Vector Reset Vector Reserved User ROM Reserved User ROM
PAGE 1 "STATIC"
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MEMORY SPACES (Continued) Data Space The instruction set of the ST6369 Core operates on a specific space, named Data Space that contains all the data necessary for the processing of the program. The Data Space allows the adFigure 12. Data Space dressing of RAM (256 bytes), EEPROM (384 bytes), ST6369 Core/peripheral registers, and read-only data such as constants and the look-up tables. Figure 13. Data Space (Continued)
b7
b0 000H DATA RAM/EEPROM BANK AREA 03FH 040H DATA ROM WINDOW AREA X REGISTER Y REGISTER V REGISTER W REGISTER DATA RAM 07FH 080H 081H 082H 083H 084H 0BFH 0C0H 0C1H 0C2H 0C3H 0C4H 0C5H 0C6H 0C7H 0C8H 0C9H 0CAH 0CBH 0CCH 0CDH 0D1H 0D2H 0D3H 0D4H 0D5H 0D7H 0D8H
b7
b0 RESERVED TIMER 2 PRESCALER REGISTER TIMER 2 COUNTER REGISTER TIMER 2 STATUS CONTROL REG. RESERVED
0D9H 0DAH 0DBH 0DCH 0DDH 0DFH 0E0H 0E1H 0E2H 0E3H 0E4H 0E5H 0E6H 0E7H 0E8H 0E9H 0EAH 0EBH 0ECH 0EDH 0EEH 0EFH 0F0H 0FEH 0FFH
PORT A DATA REGISTER PORT B DATA REGISTER PORT C DATA REGISTER RESERVED PORT A DIRECTION REGISTER PORT B DIRECTION REGISTER PORT C DIRECTION REGISTER RESERVED INTERRUPT OPTION REGISTER DATA ROM WINDOW REGISTER PROGRAM ROM PAGE REGISTER RESERVED SPI DATA REGISTER RESERVED TIMER 1 PRESCALER REGISTER TIMER 1 COUNTER REGISTER TIMER 1 STATUS/CONTROL REG. RESERVED WATCHDOG REGISTER
DA0 DATA/CONTROL REGISTER DA1 DATA/CONTROL REGISTER DA2 DATA/CONTROL REGISTER DA3 DATA/CONTROL REGISTER AD, HSYNC RESULT REGISTER OUTPUTS CONTROL REGISTER DA4 DATA/CONTROL REGISTER DA5 DATA/CONTROL REGISTER DATA RAM BANK REGISTER DEDIC. LATCHES CONTROL REG. EEPROM CONTROL REGISTER SPI CONTROL REGISTER 1 SPI CONTROL REGISTER 2 RESERVED HDA DATA REGISTER 1 HDA DATA REGISTER 2 RESERVED ACCUMULATOR
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MEMORY SPACES (Continued) Data ROM Addressing. All the read-only data are physically implemented in the ROM in which the Program Space is also implemented. The ROM therefore contains the program to be executed and also the constants and the look-up tables needed for the program. The locations of Data Space in which the different constants and look-up tables are addressed by the ST6369 Core can be considered as being a 64-byte window through which it is possible to access to the read-only data stored in the ROM. This window is located from the 40H address to the 7FH address in the Data space and allows the direct reading of the bytes from the 000H address to the 03FH address in the ROM. All the bytes of the ROM can be used to store either instructions or read-only data. Indeed, the window can be moved by step of 64 bytes along the ROM in writing the appropriate code in the Write-only Data ROM Window register (DRWR, location C9H). The effective address of the byte to be read as a data in the ROM is obtained by the concatenation of the 6 less significant bits of the address in the Data Space (as less significant bits) and the content of the DRWR (as most significant bits). So when addressing location 40H of data space, and 0 is loaded in the DRWR, the physical addressed location in ROM is 00H. Figure 14. Data ROM Window Register
DWR Data ROM Window Register (C9H, Write Only) D7 D6 D5 D4 D3 D2 D1 D0
DWR0 = Data DWR1 = Data DWR2 = Data DWR3 = Data DWR4 = Data DWR5 = Data DWR6 = Data UNUSED ROM Window 0 ROM Window 1 ROM Window 2 ROM Window 3 ROM Window 4 ROM Window 5 ROM Window 6
DWR6-DWR0. These are the Data Rom Window bits that correspond to the upper bits of data ROM program space. This register is undefined after reset. Note. Care is required when handling the DRWR as it is write only. For this reason, it is not allowed to change the DRWR contents while executing interrupts drivers, as the driver cannot save and than restore its previous content. If it is impossible to avoid the writing of this register in interrupts drivers, an image of this register must be saved in a RAM location, and each time the program writes the DRWR it writes also the image register. The image register must be written first, so if an interrupt occurs between the two instructions the DRWR register is not affected.
Figure 15. Data ROM Window Memory Addressing
DATA ROM 13 12 6 11 5 10 4 9 3 8 2 7 1 6 0 5 0 1 4 3 2 1 5 4 3 2 1 0 PROGRAM SPACE ADDRESS READ 0 DATA SPACE ADDRESS 40h-7Fh IN INSTRUCTION
WINDOW REGISTER 7 CONTENTS (DWR)
Example:
DWR=28h 0 0 1 0 1 0 0 0 0 1 0 1 1 0 0 1 DATA SPACE ADDRESS 59h
ROM ADDRESS:A19h
0
0
1
0
1
0
0
0
0
1
1
0
0
1
VR01573B
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MEMORY SPACES (Continued) Data RAM/EEPROM In the ST6369 64 bytes of data RAM are directly addressable in the data space from 80H to BFH addresses. The additional 192 bytes of RAM, the 384 bytes of EEPROM can be addressed using the banks of 64 bytes located between addresses 00H and 3FH. The selection of the bank is done by programming the Data RAM Bank Register (DRBR) located at the E8H address of the Data Space. In this way each bank of RAM, EEPROM can select 64 bytes at a time. No more than one bank should be set at a time. Figure 16. Data RAM Bank Register
DRBR Data RAM Bank Register (E8H, Write Only) D7 D6 D5 D4 D3 D2 D1 D0
DRBR0 DRBR1 DRBR2 DRBR3 DRBR4 DRBR5 DRBR6 DRBR7
DRBR7,DRBR1,DRBR0. These bits select the EEPROM pages. DRBR4,DRBR3,DRBR2. Each of these bits, when set, will select one RAM page. This register is undefined after reset. Table 5 summarizes how to set the Data RAM Bank Register in order to select the various banks or pages. Note : Care is required when handling the DRBR as it is write only. For this reason, it is not allowed to change the DRBR contents while executing interrupts drivers, as the driver cannot save and than restore its previous content. If it is impossible to avoid the writing of this register in interrupts drivers, an image of this register must be saved in a RAM location, and each time the program writes the DRBR it writes also the image register. The image register must be written first, so if an interrupt occurs between the two instructions the DRBR is not affected. EEPROM Description The data space of ST6369 family from 00H to 3FH is paged as described in Table 5. 384 bytes of EEPROM located in six pages of 64 bytes (pages 0,1,2,3,4 and 5, see Table 5).
Table 5. Data RAM Bank Register Set-up
DRBR Value Hex. 01H 02H 03H 81H 82H 83H 04H 08H 10H Binary 0000 0001 0000 0010 0000 0011 1000 0001 1000 0010 1000 0011 0000 0100 0000 1000 0001 0000 EEPROM Page 0 EEPROM Page 1 EEPROM Page 2 EEPROM Page 3 EEPROM Page 4 EEPROM Page 5 RAM Page 2 RAM Page 3 RAM Page 4 Selection
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MEMORY SPACES (Continued) Through the programming of the Data RAM Bank Register (DRBR=E8H) the user can select the bank or page leaving unaffected the way to address the static registers. The way to address the "dynamic" page is to set the DRBR as described in Table 5 (e.g. to select EEPROM page 0, the DRBR has to be loaded with content 01H, see Data RAM/EEPROM addressing for additional information). Bits 0, 1 and 7 of the DRBR are dedicated to the EEPROM. The EEPROM pages do not require dedicated instructions to be accessed in reading or writing. The EEPROM is controlled by the EEPROM Control Register (EECR=EAH). Any EEPROM location can be read just like any other data location, also in terms of access time. To write an EEPROM location takes an average time of 5 ms (10ms max) and during this time the EEPROM is not accessible by the Core. A busy flag can be read by the Core to know the EEPROM status before trying any access. In writing the EEPROM can work in two modes: Byte Mode (BMODE) and Parallel Mode (PMODE). The BMODE is the normal way to use the EEPROM and consists in accessing one byte at a time. The PMODE consists in accessing 8 bytes per time. D7. Not used SB. WRITE ONLY. If this bit is set the EEPROM is disabled (any access will be meaningless) and the power consumption of the EEPROM is reduced to the leakage values. Figure 17. EEPROM Control Register
EECR EEPROM Control Register (EAH, Read/Wr ite) D7 D6 D5 D4 D3 D2 D1 D0
EN = EEPROM Enable Bit BS = EEPROM Busy Bit PE = Parallel Mode Enable Bit PS = Parallel Start Bit Reserved (Must be set Low) Reserved (Must be set Low) SB = Stand-by Enable Bit Unused
D5, D4. Reserved for testing purposes, they must be set to zero. PS. SET ONLY. Once in Parallel Mode, as soon as the user software sets the PS bit the parallel writing of the 8 adjacent registers will start. PS is internally reset at the end of the programming procedure. Note that less than 8 bytes can be written; after parallel programming the remaining undefined bytes will have no particular content. PE. WRITE ONLY. This bit must be set by the user program in order to perform parallel programming (more bytes per time). If PE is set and the "parallel start bit" (PS) is low, up to 8 adjacent bytes can be written at the maximum speed, the content being stored in volatile registers. These 8 adjacent bytes can be considered as row, whose A7, A6, A5, A4, A3 are fixed while A2, A1 and A0 are the changing bytes. PE is automatically reset at the end of any parallel programming procedure. PE can be reset by the user software before starting the programming procedure, leaving unchanged the EEPROM registers. BS. READ ONLY. This bit will be automatically set by the CORE when the user program modifies an EEPROM register. The user program has to test it before any read or write EEPROM operation; any attempt to access the EEPROM while "busy bit" is set will be aborted and the writing procedure in progress completed. EN. WRITE ONLY. This bit MUST be set to one in order to write any EEPROM register. If the user program will attempt to write the EEPROM when EN= "0" the involved registers will be unaffected and the "busy bit" will not be set. AfterRESET thecontent of EECR registerwill be00H. Notes : When the EEPROM is busy (BS="1") the EECR can not be accessed in write mode, it is only possible to read BS status. This implies that as long as the EEPROM is busy it is not possible to change the status of the EEPROM control register. EECR bits 4 and 5 are reserved for test purposes, and must never be set to "1". Additional Notes on Parallel Mode. If the user wants to perform a parallel programming the first action should be the set to one the PE bit; from this moment the first time the EEPROM will be addressed in writing, the ROW address will be latched and it will be possible to change it only at the end of the programming procedure or by reset-
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MEMORY SPACES (Continued) ting PE without programming the EEPROM. After the ROW address latching the Core can "see" just one EEPROM row (the selected one) and any attempt to write or read other rows will produce errors. Do not read the EEPROM while PE is set. As soon as PE bit is set, the 8 volatile ROW latches are cleared. From this moment the user can load data in the whole ROW or just in a subset. PS setting will modify the EEPROM registers corresponding to the ROW latches accessed after PE. For example, if the software sets PE and accesses EEPROM in writing at addresses 18H,1AH,1BHand then sets PS, thesethree registers will be modified at the same time; the remaining bytes will have no particular content. Note that PE is internally reset at the end of the programming procedure. This implies that the user must set PE bit between two parallel programming procedures. Anyway the user can set and then reset PE without performing any EEPROMprogramming. PS is a set only bit and is internally reset at the end of the programming procedure. Note that if the user tries to set PS while PE is not set there will not be any programming procedure and the PS bit will be unaffected. Consequently PS bit can not be set if EN is low. PS can be affected by the user set if, and only if, EN and PE bits are also set to one.
INTERRUPT The ST6369 Core can manage 4 different maskable interrupt sources, plus one non-maskable interrupt source (top priority level interrupt). Each source is associated with a particular interrupt vector that contains a Jump instruction to the related interrupt service routine. Each vector is located in the Program Space at a particular address (see Table 6). When a source provides an interrupt request, and the request processing is also enabled by the ST6369 Core, then the PC register isloaded with the address of the interrupt vector (i.e. of the Jump instruction). Finally, the PC is loaded with the address of the Jump instruction and the interrupt routine is processed. The relationship between vector and source and the associated priority is hardware fixed for the different ST638x devices. For some interrupt sources it is also possible to select by software the kind of event that will generate the interrupt. All interrupts can be disabled by writing to the GEN bit (global interrupt enable) of the interrupt option register (address C8H). After a reset, ST6369 is in non maskable interrupt mode, so no interrupts will be accepted and NMI flags will be used, until a RETI instruction is executed. If an interrupt is executed, one special cycle is made by the core, during that the PC is set to the related interrupt vector address. A jump instruction at this address has to redirect program execution to the beginning of the related interrupt routine. The interrupt detecting cycle, also resets the related interrupt flag (not available to the user), so that another interrupt can be stored for this current vector, while its driver is under execution. If additional interrupts arrive from the same source, they will be lost. NMI can interrupt other interrupt routines at any time, while other interrupts cannot interrupt each other. If more than one interrupt is waiting for service, they are executed according to their priority. The lower the number, the higher the priority. Priority is, therefore, fixed. Interrupts are checked during the last cycle of an instruction (RETI included). Level sensitive interrupts have to be valid during this period. Table 6 details the different interrupt vectors/sources relationships. Interrupt Vectors/Sources The ST6369 Core includes 5 different interrupt vectors in order to branch to 5 different interrupt routines. The interrupt vectors are located in the fixed (or static) page of the Program Space.
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INTERRUPT (Continued) Table 6. Interrupt Vectors/Sources Relationships
Interrupt Source PC6/IRIN Pin (1) Timer 2 Vsync Timer 1 PC4/PWRIN Associated Vector Interrupt Vector # 0 (NMI) Interrupt Vector # 1 Interrupt Vector # 2 Interrupt Vector # 3 Interrupt Vector # 4 Vector Address 0FFCH-0FFDH 0FF6H-0FF7H 0FF4H-0FF5H 0FF2H-0FF3H 0FF0H-0FF1H
IOR Interr upt Option Register (C8H, Write Only) D7 D6 D5 D4 D3 D2 D1 D0
Interrupt Option Register The Interrupt Option Register (IOR register, location C8H) is used to enable/disable the individual interrupt sources and to select the operating mode of the external interrupt inputs. This register can be addressed in the Data Space as RAM location at the C8H address, nevertheless it is write-only register that can not be accessed with single-bit operations. The operating modes of the external interrupt inputs associated to interrupt vectors #1 and #2 are selected through bits 4 and 5 of the IOR register. Figure 18. Interrupt Option Register
Note: 1. This pin is associated with the NMI Interrupt Vector
The interrupt vector associated with the non-maskable interrupt source is named interrupt vector #0. It is located at the (FFCH,FFDH) addresses in the Program Space. This vector is associated with the PC6/IRIN pin. The interrupt vectors located at addresses (FF6H,FF7H), (FF4H,FF5H), (FF2H,FF3H), (FF0H,FF1H) are named interrupt vectors #1, #2, #3 and #4 respectively. These vectors are associated with TIMER 2 (#1), VSYNC (#2), TIMER 1 (#3) and PC4(PWRIN) (#4). Interrupt Priority The non-maskable interrupt request has the highest priority and can interrupt any other interrupt routines at any time, nevertheless the other interrupts cannot interrupt each other. If more than one interrupt request is pending, they are processed by the ST6369 Core according to their priority level: vector #1 has the higher priority while vector #4 the lower. The priority of each interrupt source is hardware fixed.
Unuse d GEN = Global Enab le Bit ES2 = Edge Selection Bit EL1 = Edge Level Selection Bit Unuse d
D7. Not used. EL1. This is the Edge/Level selection bit of interrupt #1. When set to one, the interrupt is generated on low level of the related signal; when cleared to zero, the interrupt is generated on falling edge. The bit is cleared to zero after reset. ES2. This is the edge selection bit on interrupt #2. This bit is used on the ST6369 devices with on-chip OSD generator for VSYNC detection. GEN. This is the global enable bit. When set to one all interrupts are globally enabled; when this bit is cleared to zero all interrupts are disabled (excluding NMI). D3 - D0. These bits are not used.
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INTERRUPT (Continued) Interrupt Procedure The interrupt procedure is very similar to a call procedure; the user can consider the interrupt as an asynchronous call procedure. As this is an asynchronous event the user does not know about the context and the time at which it occurred. As a result the user should save all the data space registers which will be used inside the interrupt routines. There are separate sets of processor flags for normal, interrupt and non-maskable interrupt modes which are automatically switched and so these do not need to be saved. The following list summarizes the interrupt procedure (refer also to Figure 19. Interrupt Processing Flow Chart): - Interrupt detection C main are ex- The flagswithand Z of the and Z routineinterrupt changed the flags C of the routine (resp. the NMI flags) - The value of the PC is stored in the first level of the stack - The normal interrupt lines are inhibited (NMI still active) - The edge flip-flop is reset - The related interrupt vector is loaded in the PC. are saved inside the in- User selected registers(normally on a software terrupt service routine stack) the interrupt found by - The source ofone source isisassociated polling (if more than to the same vector) - Interrupt servicing - Return from interrupt (RETI) switches back - Automatically the ST63xx core interrupt flags) to the normal flags (resp the and pops the previous PC value from the stack The interrupt routine begins usually by the identification of the device that has generated the interrupt request. The user should save the registers which are used inside the interrupt routine (that holds relevant data) into a software stack. After the RETI instruction execution, the Core carries out the previous actions and the main routine can continue. ST6369 Interrupt Details IR Interrupt (#0). The IRIN/PC6 Interrupt is connected to the first interrupt #0 (NMI, 0FFCH). If the IRINT interrupt is disabled at the Latch circuitry, then it will be high. The #0 interrupt input detects a Figure 19. Interrupt Processing Flow-Chart
INSTRUCTION
FE TCH INST RUCTION
EX ECUTE INST RUCTION
WA S THE INST RUCTION A RETI YE S YES
NO
LOAD PC FROM INTERRUPT VECTOR ( FF C / FFD )
?
NO
IS THE CORE ALREADY IN NORMAL MODE ?
SET INTE RRUPT MAS K
CLEA R INTERRUPT MAS K
PUSH THE PC INTO THE STAC K
SELECT PROGRAM FLA GS
SEL ECT INTERNAL MODE FLAG
" POP " THE STACK ED PC CHECK IF THERE IS AN INTERRUPT REQUES T AND INTE RRUPT MASK YES
NO
?
VA000014
high to low level. Note that once #0 has been latched, then the only way to remove the latched #0 signal is to service the interrupt. #0 can interrupt the other interrupts. A simple latch is provided from the PC6(IRIN) pin in order to generate the IRINT signal. This latch can be triggered by either the positive or negative edge of IRIN signal. IRINT is inverted with respect to the latch. The latch can be read by software and reset by software.
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INTERRUPT (Continued) TIMER 2 Interrupt (#1). The TIMER 2 Interrupt is connectedto the interrupt #1 (0FF6H). The TIMER 2 interrupt generates a low level (which is latched in the timer). Only the low level selection for #1 can be used. Bit 6 of the interrupt option register C8H has to be set. VSYNC Interrupt (#2). The VSYNC Interrupt is connected to the interrupt #2. When disabled the VSYNC INT signal is low. The VSYNC INT signal is inverted with respect to the signal applied to the VSYNC pin. Bit 5 of the interrupt option register C8H is used to select the negative edge (ES2=0) or the positive edge (ES2=1); the edge will depend on the application. Note that once an edge has been latched, then the only way to remove the latched signal is to service the interrupt. Care must be taken not to generate spurious interrupts. This interrupt may be used for synchronize to the VSYNC signal in order to change characters in the OSD only when the screen is on vertical blanking (if desired). This method may also be used to blink characters. TIMER 1 Interrupt (#3). The TIMER 1 Interrupt is connected to the fourth interrupt #3 (0FF2H) which detects a low level (latched in the timer). PWR Interrupt (#4). The PWR Interrupt is connected to the fifth interrupt #4 (0FF0H). If the PWRINT is disabled at the PWR circuitry, then it will be high. The #4 interrupt input detects a low level. A simple latch is provided from the PC4 (PWRIN)pin in order to generate the PWRINT signal. This latch can be triggered by either the positive or negative edge of the PWRIN signal. PWRINT is inverted with respect to the latch. The latch can be reset by software. Notes Global disable does not reset edge sensitive interrupt flags. These edge sensitive interrupts become pending again when global disabling is released. Moreover, edge sensitive interrupts are stored in the related flags also when interrupts are globally disabled, unless each edge sensitive interrupt is also individually disabled before the interrupting event happens. Global disable is done by clearing the GEN bit of Interrupt option register, while any individual disable is done in the control register of the peripheral. The on-chip Timer peripherals have an interrupt requestflag bit (TMZ), this bit is set to one when the device wants to generate an interrupt request and a mask bit (ETI) that must be set to one to allow the transfer of the flag bit to the Core.
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RESET The ST6369 devices can be reset in two ways: by the external reset input (RESET) tied low and by the hardware activated digital watchdog peripheral. RESET Input The externalactive low reset pin is used to reset the ST6369 devices and provide an orderly software startup procedure. The activation of the Reset pin may occur at any time in the RUN or WAIT mode. Even short pulses at the reset pin will be accepted since the reset signal is latched internally and is only cleared after 2048 clocks at the oscillator pin. The clocks from the oscillator pin to the reset circuitry are bufferedby a schmitt trigger so that an oscillator in start-up conditions will not give spurious clocks. When the reset pin is held low, the external crystal oscillator is also disabled in order to reduce current consumption. The MCU is configured in the Reset mode as long as the signal of the RESET pin is low. The processing of the program is stopped and the standard Input/Output ports (port A, port B and port C) are in the input state. As soon as the level on the reset pin becomes high, the initialization sequenceis executed. Refer to the MCU initialization sequence for additional information.
Watchdog Reset The ST6369 devices are provided with an on-chip hardware activated digital watchdog function in order to provide a graceful recovery from a software upset. If the watchdog register is not refreshed and the end-of-count is reached, then the reset state will be latched into the MCU and an internal circuit pulls down the reset pin. This also resets the watchdog which subsequently turns off the pulldown and activates the pull-up device at the reset pin. This causes the positive transition at the reset pin. The MCU will then exit the reset state after 2048 clocks on the oscillator pin. Application Notes An external resistor between VDD and the reset pin is not required because an internal pull-up device is provided. The user may prefer to add an external pull-up resistor. An internal Power-on device does not guarantee that the MCU will exit the reset state when VDD is above 4.5V and therefore the RESET pin should be externally controlled.
Figure 20. Internal Reset Circuit
OSCILLATOR SIGNAL COUNTER
1.0k
ST6 INTERNAL RESET
TO ST6
RESET (ACTIVE LOW) VDD 300k
RESET
WATCHDOG RESET
VA000200
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RESET (Continued) Figure 21. Reset & Interrupt Processing Flow-Chart Figure 22. Restart Initialization Program Flow-Chart
RESET
RESET
JP
JP: 2 BYTES/4 CYCLES
RESET VECTOR
NMI MASK SET INT LATCH CLEARED ( IF PRESENT )
INITIALIZATION ROUTINE
SELECT NMI MODE FLAGS
RETI
RETI: 1BYTES/2 CYCLES
PUT FFEh ON ADDRESS BUS
VA00 0181
YES
IS RESET STILL PRESENT ?
NO
LOAD PC FROM RESET LOCATIONS FFE / FFF
FETCH INSTRUCTION
VA000427
MCU InitializationSequence When a reset occurs the stack is reset to program counter, the PC is loaded with the address of the reset vector (located in the program ROM at addresses FFEH & FFFH). A jump instruction to the
beginning of the program has to be written into these locations.After a reset the interrupt mask is automatically activated so that the Core is in nonmaskable interrupt mode to prevent false or ghost interrupts during the restart phase. Therefore the restart routine should be terminated by a RETI instruction to switch to normal mode and enable interrupts. If no pending interrupt is present at the end of the reset routine, the ST6369 will continue with the instruction after the RETI; otherwise the pending interrupt will be serviced. RESET Low Power Mode When the reset pin is low, the quartz oscillator is Disabled allowing reduced current consumption. When the reset pin is raised the quartz oscillator is enabled and oscillations will start to build up.The internal reset circuitry will count 2048 clocks on the oscillator pin before allowing the MCU to go out of the reset state;the clocks are after a schmitt trigger so that false or multiple counts are not possible.
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WAIT & STOP MODES The STOP and WAIT modes have been implemented in the ST6369 Core in order to reduce the consumption of the device when the latter has no instruction to execute. These two modes are described in the following paragraphs. On ST6369 as the hardware activated digital watchdog function is present the STOP instruction is de-activated and any attempt to execute it will cause the automatic execution of a WAIT instruction. WAIT Mode The configuration of the MCU in the WAIT mode occurs as soon as the WAIT instruction is executed. The microcontroller can also be considered as being in a "software frozen" state where the Core stops processing the instructions of the routine, the contents of the RAM locations and peripheral registers are saved as long as the power supply voltage is higher than the RAM retention voltage but where the peripheralsare still working. The WAIT mode is used when the user wants to reduce the consumption of the MCU when it is in idle, while not losing count of time or monitoring of external events. The oscillator is not stopped in order to provide clock signal to the peripherals. The timers counting may be enabled (writing the PSI bit in TSCR register) and the timer interrupt may be also enabled before entering the WAIT mode; this allows the WAIT mode to be left when timer interrupt occurs. If the exit from the WAIT mode is performed with a general RESET (either from the activation of the external pin or by watchdog reset) the MCU will enter a normal reset procedure as described in the RESET chapter. If an interrupt is generated during WAIT mode the MCU behaviour depends on the state of the ST6369 Core before the initialization of the WAIT sequence, but also of the kind of the interrupt request that is generated. This case will be described in the following paragraphs. In any case, the ST6369 Core does not generate any delay after the occurrence of the interrupt because the oscillator clock is still available. STOP Mode On ST6369 the hardware watchdog is present and the STOP instruction has been de-activated. Any attempt to execute a STOP will cause the automatic execution of a WAIT instruction. Exit from WAIT Mode The following paragraphs describe the output procedure of the ST6369 Core from WAIT mode when
an interrupt occurs. It must be noted that the restart sequence depends on the original state of the MCU (normal, interrupt or non-maskable interrupt mode) before the start of the WAIT sequence, but also of the type of the interrupt request that is generated. In all cases the GEN bit of IOR has to be set to 1 in order to restart from WAIT mode. Contrary to the operation of NMI in the run mode, the NMI is masked in WAIT mode if GEN=0. Normal Mode. If the ST6369 Core was in the main routinewhen the WAIT instruction has been executed, the ST6369 Core outputsfrom the wait mode as soon as any interrupt occurs; the related interrupt routine is executedand at the end of the interruptservice routine the instruction that follows the WAIT instruction is executedif no other interrupts are pending. Non-maskable Interrupt Mode. If the WAIT instruction has been executed during the execution of the non-maskable interrupt routine, the ST6369 Core outputs from the wait mode as soon as any interrupt occurs: the instruction that follows the WAIT instruction is executed and the ST6369 Core is still in the non-maskable interrupt mode even if another interrupt has been generated. Normal Interrupt Mode. If the ST6369 Core was in the interrupt mode before the initialization of the WAIT sequence, it outputs from the wait mode as soon as any interrupt occurs. Nevertheless, two cases have to be considered: - If the interrupt is a normal interrupt, the interrupt routine in which the WAIT was entered will be completed with the execution of the instruction that follows the WAIT and the ST6369 Core is still in the interrupt mode. At the end of this routine pending interrupts will be serviced in accordance to their priority. - If the interrupt is a non-maskable interrupt, the non-maskable routine is processed at first. Then, the routine in which the WAIT was entered will be completed with the execution of the instruction that follows the WAIT and the ST6369 Core is still in the normal interrupt mode. Notes : If all the interrupt sources are disabled, the restart of the MCU can only be done by a Reset activation. The Wait instruction is not executed if an enabled interrupt request is pending. In the ST6369 the hardware activated digital watchdog function is present. As the watchdog is always activated the STOP instruction is de-activated and any attempt to execute the STOP instruction will cause an execution of a WAIT instruction.
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ON-CHIP CLOCK OSCILLATOR The internal oscillator circuit is designed to require a minimum of external components. A crystal quartz, a ceramic resonator, or an external signal (provided to the OSCIN pin) may be used to generate a system clock with various stability/cost tradeoffs. The typical clock frequency is 8MHz. Please note that different frequencies will affect the operation of those peripherals (D/As, SPI) whose reference frequencies are derived from the system clock. The different clock generator options connection methods are shown in Figures 23 and 24. One machine cycle takes 13 oscillator pulses; 12 clock pulses are needed to increment the PC while and additional 13th pulse is needed to stabilize the internal latches during memory addressing. This means that with a clock frequency of 8MHz the machine cycle is 1.625Sec. The crystal oscillator start-up time is a function of many variables: crystal parameters (especially RS), oscillator load capacitance (CL), IC parameters, ambient temperature, and supply voltage.It must be observed that the crystal or ceramic leads and circuit connections must be as short as possible. Typical values for CL1 and CL2 are in the range of 15pF to 22pF but these should be chosen based on the crystal manufacturers specification. Typical input capacitance for OSCIN and OSCOUT pins is 5pF. The oscillator output frequency is internallydivided by 13 to produce the machine cycle and by 12 to produce the Timer and the Watchdog clock. A byte cycle is the smallest unit needed to execute any operation (i.e., increment the program counter). An instruction may need two, four, or five byte cycles to be executed (See Table 7). Table 7. Intructions Timing with 8MHz Clock
Instruction Type Branch if set/reset Branch & Subroutine Branch Bit Manipulation Load Instruction Arithmetic & Logic Conditional Branch Program Control Cycles 5 Cycles 4 Cycles 4 Cycles 4 Cycles 4 Cycles 2 Cycles 2 Cycles Execution Time 8.125s 6.50s 6.50s 6.50s 6.50s 3.25s 3.25s
Figure 23. Clock Generator Option (1)
Figure 24. Clock Generator Option (2)
Figure 25. OSCIN, OSCOUT Diagram
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INPUT/OUTPUT PORTS The ST6369 microcontrollers use three standard I/O ports (A,B,C) with up to eight pins on each port; refer to the device pin configurations to see which pins are available. Each line can be individually programmed either in the input mode or the output mode as follows by software. - Output - Input with on-chip pull-up resistor (selected by software) - Input without on-chip pull-up resistor (selected by software) Note: pins with 12V open-drain capability do not have pull-up resistors. In output mode the following hardware configurations are available: - Open-drain output 12V (PA4-PA7, PC4-PC7) - Open-drain output 5V (PC0-PC3) - Push-pull output (PA0-PA3, PB0-PB6) The lines are organized in three ports (port A,B,C). The ports occupy 6 registers in the data space. Each bit of these registers is associated with a particular line (for instance, the bits 0 of the Port A Data and Direction registers are associated with the PA0 line of Port A). There are three Data registers (DRA, DRB, DRC), that are used to read the voltage level values of the lines programmed in the input mode, or to write the logic value of the signal to be output on the lines configured in the output mode. The port Data Registers can be read to get the effective logic levels of the pins, but they can be also written by the user software, in conjunction with the related Data Direction Register, to select the different input mode options. Single-bit operations on I/O registers (bit set/reset instructions) are possible but care is necessary because reading in input mode is made from I/O pins and therefore might be influenced by the external load, while writing will directly affect the Port data register causing an undesired changes of the input configuration. The three Data Direction registers (DDRA, DDRB, DDRC) allow the selection of the direction of each pin (input or output). All the I/O registers can be read or written as any other RAM location of the data space, so no extra RAM cell is needed for port data storing and manipulation. During the initialization of the MCU, all the I/O registers are cleared and the input mode with pull-up is selected on all the pins thusavoiding pin conflicts(with the exception of PC2 that is set in output mode and is set high ie. high impedance).
Details of I/O Ports When programmed as an input a pull-up resistor (if available) can be switched active under program control. When programmed as an output the I/O port will operate either in the push-pull mode or the open-drain mode according to the hardware fixed configuration as specified below. Port A. PA0-PA3 are available as push-pull when outputs. PA4-PA7 are available as open-drain (no push-pull programmability) capable of withstanding 12V (no resistive pull-up in input mode). PA6PA7 has been specially designed for higher driving capability and are able to sink 25mA with a maximum VOL of 1V. Port B. All lines are configured as push-pull when outputs. Port C. PC0-PC3 are available as open-drain capable of withstanding a maximum VDD+0.3V. PC4PC7 are available as open-drain capable of withstanding 12V (no resistive pull-up in input mode). Some lines are also used as I/O buffers for signals coming from the on-chip SPI. In this case the final signal on the output pin is equivalent to a wired AND with the programmed data output. If the user needs to use the serial peripheral, the I/O line should be set in output mode while the open-drain configuration is hardware fixed; the corresponding data bit must set to one. If the latchedinterrupt functionsare used (HSYNC, PWRIN) then the corresponding pins should be set to input mode. On ST6369 the I/O pins with double or special functions are: - PC0/SCL (connected to the SPI clock signal) - PC1/SDA (connected to the SPI data signal) - PC3/SEN (connected to the SPI enable signal) - PC4/PWRIN (connected to the PWRIN interrupt latch) - PC6/HSYNC (connected to the HSYNC interrupt latch) All the Port A,B and C I/O lines have Schmitt-trigger input configuration with a typical hysteresis of 1V.
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INPUT/OUTPUT PORTS (Continued) Table 8. I/O Port Options Selection
DDR 0 0 1 DR 0 1 X Mode Input Input Output Option With on-chip pull-up resistor Without on-chip pull-up resistor Open-drain or Push-Pull
I/O Pin Programming Each pin can be individually programmed as input or output with different input and output configurations. This is achieved by writing to the relevant bit in the data (DR) and data direction register (DDR). Table 8 shows all the port configurations that can be selected by the user software.
Note: X: Means don't care.
Figure 27. Port A, B, C Data Register
DDRA, DDRB,DDRC Port A, B, C Data Direction Register ( C4H PA, C5H PB, C6H PC Read/ Write ) D7 D6 D5 D4 D3 D2 D1 D0
Figure 26. Port A, B, C Data Register
DRA, DRB, DRC Port A, B, C Data Register ( C0H PA, C1H PB, C2H PC Read/ Write ) D7 D6 D5 D4 D3 D2 D1 D0
PA0 - PA7 = Data Bits PB0 - PB7 = Data Bits PC0 - PC7 = Data Bits
PA0 - PA7 = Data Direction Bits PB0 - PB7 = Data Direction Bits PC0 - PC7 = Data Direction Bits "0" Defines bit as Inpu t "1" Defines bit as Outpu t
PA7-PA0. These are the I/O port A data bits. Reset at power-on. PB7-PB0.These are the I/O port B data bits. Reset at power-on. PC7-PC0. Set to 04H at power-on. Bit 2 (PC2 pin) is set to one (open drain therefore high impedence).
PA7-PA0. These are the I/O port A data direction bits. When a bit is cleared to zero the related I/O line is in input mode, if bit is set to one the related I/O line is in output mode. Reset at power-on. PB7-PB0. These are the I/O port B data direction bits. When a bit is cleared to zero the related I/O line is in input mode, if bit is set to one the related I/O line is in output mode. Reset at power-on. PC7-PC0. These are the I/O port C data direction bits. When a bit is cleared to zero the related I/O line is in input mode, if bit is set to one the related I/O line is in output mode. Set to 04H at power-on. Bit 2 (PC2 pin) is set to one (output mode selected).
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INPUT/OUTPUT PORTS (Continued) Input/Output Configurations The following schematics show the I/O lines hardware configuration for the different options. Figure 28 shows the I/O configuration for an I/O pin with open-drain 12V capability (standard drive and high drive). Figure 29 shows the I/O configuration for an I/O pin with push-pull and with open drain 5V capability. Figure 28. I/O Configuration Diagram (Open Drain 12V) Notes : The WAIT instruction allows the ST6369 to be used in situations where low power consumption is needed. This can only be achieved however if the I/O pins either are programmed as inputs with well defined logic levels or have no power consuming resistive loads in output mode. The unavailable I/O lines PB0, PB3 and PB7 should be programmed in output mode. Single-bit operations on I/O registers are possible but care is necessary because reading in input mode is made from I/O pins while writing will directly affect the Port data register causing an undesired changes of the input configuration.
Figure 29. I/O Configuration Diagram (Open Drain 5V, Push-pull)
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TIMERS The ST6369 devices offer two on-chip Timer peripherals consisting of an 8-bit counter with a 7-bit programmable prescaler, thus giving a maximum count of 215, and a control logic that allows configuring the peripheral operating mode. Figure 30 shows the timer block diagram. The content of the 8-bit counters can be read/written in the Timer/Counter registers TCR that can be addressed in the data space as RAM location at addresses D3H (Timer 1) and DBH (Timer 2). The state of the 7-bit prescaler can be read in the PSC register at addresses D2H (Timer 1) and DAH (Timer 2). The control logic is managed by TSCR registers at D4H (Timer 1) and DCH (Timer 2) addressesas described in thefollowing paragraphs. The following description applies to both Timer 1 and Timer 2. The 8-bit counter is decrement by the output (rising edge) coming from the 7-bit prescaler and can be loaded and read under program control. When it decrements to zero then the TMZ (timer zero) bit in the TSCR is set to one. If the ETI (enable timer interrupt) bit in the TSCR is also set to one an interrupt request, associated to interrupt vector #3 (for Timer 1) and #1 for Timer 2, is generated. The interrupt of the timer can be used to exit the MCU from the WAIT mode.
The prescaler decrements on rising edge. The prescaler input is the oscillator frequency divided by 12. Depending on the division factor programmed by PS2/PS1/PS0 (see table 9) bits in the TSCR, the clock input of the timer/counter register is multiplexed to different sources. On division factor 1, the clock input of the prescaler is also that of timer/counter; on factor2, bit 0 of prescaler register is connectedto the clock input of TCR. This bit changes its state with the half frequency of prescaler clock input. On factor 4, bit 1 of PSC is connected to clock input of TCR, and so on. On division factor 128, the MSB bit 6 of PSC is connected to clock input of TCR. The prescaler initialize bit (PSI) in the TSCR register must be set to one to allow the prescaler (and hence the counter) to start. If it is cleared to zero then all of the prescaler bits are set to one and the counter is inhibited from counting. The prescaler can be given any value between 0 and 7FH by writing to the related register address, if bit PSI in the TSCR register is set to one. The tap of the prescaler is selected using the PS2/PS1/PS0bits in the control register. Figure 31 shows the timer working principle.
Figure 30. Timer Peripheral Block Diagram
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TIMERS (Continued) Figure 31. Timer Working Principle
Timer Operating Modes As on ST6369 devices the external TIMER pin is not available the only allowed operating mode is the output mode that have to be selected by setting to 1 bit 4 and by clearing to 0 bit 5 in the TSCR1 register. This procedure will enable both Timer 1 and Timer 2. Output Mode (TSCR1 D4 = 1, TSCR1 D5 = 0). On this mode the timer prescaler is clocked by the prescaler clock input (OSC/12). The user can select the desired prescaler division ratio through the PS2/PS1/PS0 bits. When TCR count reaches 0, it sets the TMZ bit in the TSCR. The TMZ bit can be tested under program control to perform timer functions whenever it goes high. Bit D4 and D5 on TSCR2 (Timer 2) register are not implemented. Timer Interrupt When the counter register decrements to zero and the software controlled ETI (enable timer interrupt) bit is set to one then an interrupt request associ-
ated to interrupt vector #3 (for Timer 1) and to interrupt vector #1 (for Timer 2) is generated. When the counter decrements to zero also the TMZ bit in the TSCR register is set to one. Notes : TMZ is set when the counter reaches 00H ; however, it may be set by writing 00H in the TCR register or setting the bit 7 of the TSCR register. TMZ bit must be cleared by user software when servicing the timer interrupt to avoid undesired interrupts when leaving the interrupt service routine. After reset, the 8-bit counter register is loaded to FFH while the 7-bit prescaler is loaded to 7FH , and the TSCR register is cleared which means that timer is stopped (PSI=0) and timer interrupt disabled. A write to the TCR register will predominate over the 8-bit counter decrement to 00H function, i.e. if a write and a TCR register decrement to 00H occur simultaneously, the write will take precedence, and the TMZ bit is not set until the 8-bit counter reaches 00H again. The values of the TCR and the PSC registers can be read accurately at any time.
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TIMERS (Continued) Figure 32. Timer Status Control Registers
TSCR Imer 1&2 Status Control Registers DAH Timer 1, DCH Timer 2, Read/ Write D7 D6 D5 D4 D3 D2 D1 D0
The TSCR1 and TSCR2 registers are cleared on reset. The correct D4-D5 combination must be written in TSCR1 by user's software to enable the operation of Timer 1 and Timer 2. Table 9. Prescaler Division Factors
PS2 PS1 0 0 1 1 0 0 1 1 PS0 0 1 0 1 0 1 0 1 Divided By 1 2 4 8 16 32 64 128
PS0 = Prescaler Mux. Select PS1 = Prescaler Mux. Select PS2 = Prescaler Mux. Select PSI = Prescaler Initialize Bit D4 = Timers Enable Bit* D5 = Timers Enable Bit* ETI = Enable Timer Inte rrupt TMZ = Timer Zero Bit
*
0 0 0 0 1 1 1 1
Only Available in TSCR1
TMZ. Low-to-high transition indicates that the timer count register has decrement to zero. This bit must be cleared by user software before to start with a new count. ETI. This bit, when set, enables the timer interrupt (vector #3 for Timer 1, vector #1 for Timer 2) request. If ETI=0 the timer interrupt is disabled. If ETI= 1 and TMZ= 1 an interrupt request is generated. D5. This is the timers enable bit D5. It must be cleared to 0 together with a set to 1 of bit D4 to enable both Timer 1 and Timer 2 functions. It is not implemented on TSCR2 register. D4. This is the timers enable bit D4. This bit must be set to 1 together with a clear to 0 of bit D5 to enable both Timer 1 and Timer 2 functions. It is not implemented on TSCR2 register.
D5 0 0 1 D4 0 1 X Timers Disabled Enabled Reserved
Figure 33. Timer Counter Registers
TCR Timer Counter 1&2 Register D3H Timer 1, DBH Timer 2, Read/ Write D7 D6 D5 D4 D3 D2 D1 D0
D7 - D0 = Counter bits
Figure 34. Timer Counter Registers
PSC TimerPrescaler 1&2 Register D2H Timer 1, DAH Timer 2, Read/ Write D7 D6 D5 D4 D3 D2 D1 D0
PS1. Used to initialize the prescaler and inhibit its counting while PSI = 0 the prescaler is set to 7FH and the counter is inhibited. When PSI = 1 the prescaler is enabled to count downwards. As long as PSI= 0 both counter and prescaler are not running. PS2-PS0. These bits select the division ratio of the prescaler register. (see table 9)
D6 - D0 = Prescaler bits Always read as "0"
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HARDWARE ACTIVATED DIGITAL WATCHDOG FUNCTION The hardware activated digital watchdog function consists of a down counter that is automatically initialized after reset so that this function does not need to be activated by the user program. As the watchdog function is always activated this down counter can not be used as a timer. The watchdog is using one data space register (HWDR location D8H). The watchdog register is set to FEH on reset and immediately starts to count down, requiring no software start. Similarly the hardware activated watchdog can not be stopped or delayed by software. The watchdog time can be programmed using the 6 MSbits in the watchdog register, this gives the possibility to generate a reset in a time between 3072 to 196608 oscillator cycles in 64 possible steps. (With a clock frequency of 8MHz this means from 384s to 24.576ms). The reset is prevented if the register is reloaded with the desired value before bits 2-7 decrement from all zeros to all ones. The presence of the hardware watchdog deactivates the STOP instruction and a WAIT instruction is automatically executed instead of a STOP. Bit 1 of the watchdog register (set to one at reset) can be used to generate a software reset if cleared to zero). Figure 35 shows the watchdog block diagram while Figure 36 shows its workingprinciple.
Figure 36. Hardware Activated Watchdog Working Principle
Figure 35. Hardware Activated Watchdog Block Diagram
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HARDWARE ACTIVATED DIGITAL WATCHDOG FUNCTION (Continued) Figure 37. Watchdog Register
HWDR Hardware Activated Watchdog Register (D8H, Read/ Write) D7 D6 D5 D4 D3 D2 D1 D0
C = Watchdog Activation Bit SR = Software Reset Bit T1-T6 = Counter Bits
SERIAL PERIPHERAL INTERFACE The ST6369 Serial Peripheral Interface (SPI) has been designed to be cost effective and flexible in interfacing the various peripherals in TV applications. It maintains the software flexibility but adds hardware configurations suitable to drive devices which require a fast exchange of data. The three pins dedicated for serial data transfer (single master only) can operate in the following ways: - as standard I/O lines (software configuration) 2 - as S-BUS or as I CBUS (two pins) - as standard (shift register) SPI When using the hardware SPI, a fixed clock rate of 62.5kHz is provided. It has to be noted that the first bit that is output on the data line by the 8-bit shift register is the MSB. SPI Data/Control Registers For I/O details on SCL (Serial Clock), SDA (Serial Data) and SEN (Serial Enable) please refer to I/O Ports description with reference to the following registers: Port C data register, Address C2H (Read/Write). - BIT D0 "SCL" - BIT D1 "SDA" - BIT D3 "SEN" Port C data direction register, Address C6H (Read/Write). Figure 38. SPI Serial Data Register
SSDR SPI Serial Data Register (CCH, Read/ Write) D7 D6 D5 D4 D3 D2 D1 D0
T1-T6. These are the watchdog counter bits. It should be noted that D7 (T1) is the LSB of the counter and D2 (T6) is the MSB of the counter, these bits are in the opposite order to normal. SR. This bit is set to one during the reset phase and will generate a software reset if cleared to zero. C. This is the watchdog activation bit that is hardware set. The watchdog function is always activated independently of changes of value of this bit. The register reset value is FEH (Bit 1-7 set to one, Bit 0 cleared).
D0-D7 = Data Bits
D7-D0. These are the SPI data bits. They can be neither read nor written when SPI is operating (BUSY bit set). They are undefined after reset.
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SERIAL PERIPHERAL INTERFACE (Continued) Figure 39. SPI Control Register 1
SCR1 SPI Control Register 1 (EBH, Write only) D7 D6 D5 D4 D3 D2 D1 D0
S-BUS/I2C BUS Selection STD/SPI Enable STP = Stop Bit STR = Start Bit Unused
Figure 40. SPI Control Register2
SCR2 SPI Control Register 2 (ECH, Read/ Write) D7 D6 D5 D4 D3 D2 D1 D0
BSY = Busy Bit 0 ACN = Acknowledge Bit VRY/S = Verify/Sync.Enab le TX/RX = Enable Bit Unuse d
D7-D4. These bits are not used. STR. This is Start bit for I2CBUS/S-BUS. This bit is meaningless when STD/SPI enable bit is cleared to zero. If this bit is set to one STD/SPI bit is also set to "1" and SPI Start generation, before beginning of transmission, is enabled. Set to zero after reset. STP. This is Stop bit for I2CBUS/S-BUS. This bit is meaningless when STD/SPI enable bit is cleared to zero. If this bit is set to one STD/SPI bit is also set to "1" and SPI Stop condition generation is enabled. STP bit must be reset when standard protocol is used (this is also the default reset conditions). Set to zero after reset. STD, SPI Enable. This bit, in conjunction with SBUS/I2CBUS bit, allows the SPI disable and will select between I2CBUS/S-BUS and Standard shift register protocols. If this bit is set to one, it selects both I2CBUS and S-BUS protocols; final selection between them is made by SBUS/I2CBUS bit. If this bit is cleared to zero when S-BUS/I2CBUS is set to "1" the Standard shift register protocol is selected. If this bit is cleared to "0" when S-BUS/I2CBUS is cleared to 0 the SPI is disabled. Set to zero after reset. S-BUS/I2CBUS Selection. This bit, in conjunction with STD/SPI bit, allows the SPI disable and will select between I2CBUS and S-BUS protocols. If this bit is cleared to "0" when STD bit is also "0", the SPI interface is disabled. If this bit is cleared to zero when STD bit is set to "1", the I2CBUS protocol will be selected. If this bit is set to "1" when STD bit is set to "1", the S-BUS protocol will be selected. Cleared to zero after reset. Table 10. SPI Modes Selection
D1 STD/SP 0 0 1 1 D0 2 S-BUS/I C BUS 0 1 0 1 SPI Function Disabled STD Shift Reg. I2C BUS S-BUS
D7-D4. These bits are not used. TX/RX.Write Only. When this bit is set, current byte operation is a transmission. When it is reset, current operation is a reception. Set to zero after reset. VRY/S.Read Only/Write Only. This bit has two different functions in relation to read or write operation. Reading Operation: when STD and/or TRX bits is cleared to 0, this bit is meaningless. When bits STD and TX are set to 1, this bit is set each time BSY bit is set. This bit is reset during byte operation if real data on SDA line are different from the output from the shift register. Set to zero after reset. Writing Operation : it enables (if set to one) or disables (if cleared to zero) the interrupt coming from VSYNC pin. Undefined after reset. Refer to OSD description for additional information. ACN.Read Only. If STD bit (D1 of SCR1 register) is cleared to zero this bit is meaningless. When STD is set to one, this bit is set to one if no Acknowledge has been received. In this case it is automatically reset when BSY is set again. Set to zero after reset. BSY.Read/Set Only. This is the busy bit. When a one is loaded into this bit the SPI interface start the transmission of the data byte loaded into SSDR data register or receiving and building the receive data into the SSDR data register. This is done in accordance with the protocol, direction and start/stop condition(s). This bit is automatically cleared at the end of the current byte operation. Cleared to zero after reset. Note : The SPI shift register is also the data transmission register and the data received register; this feature is made possible by using the serial structure of the ST6369 and thus reducing size and complexity.
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SERIAL PERIPHERAL INTERFACE (Continued) During transmission or reception of data, all access to serial data register is therefore disabled. The reception or transmission of data is started by setting the BUSY bit to "1"; this will be automatically reset at the end of the operation. After reset, the busy bit is cleared to "0", and the hardware SPI disabled by clearing bit 0 and bit 1 of SPI control register 1 to "0". The outputs from the hardware SPI are "ANDed" to the standard I/O software controlled outputs. If the hardware SPI is in operation the Port C pins related to the SPI should be configured as outputs using the Data Direction Register and should be set high. When the SPI is configured as the S-BUS, the three pins PC0, PC1 and PC3 become the pins SCL, SDA and SEN respectively. When configured as the I2CBUS the pins PC0 and PC1 are configured as the pins SCL and SDA; PC3 is not driven and can be used as a general purpose I/O pin. In the case of the STD SPI the pins PC0 and PC1 become the signals CLOCK and DATA, PC3 is not driven and can be used as general purpose I/O pin. The VERIFY bit is available when the SPI is configured as either S-BUS or I2CBUS. At the start of a byte transmission, the verify bit is set to one. If at any time during the transmission of the following eight bits, the data on the SDA line does not match the data forced by the SPI (while SCL is high), then the VERIFY bit is reset. The verify is available only during transmission for the S-BUS and I2CBUS; for other protocol it is not defined. The SDA and SCL signal entering the SPI are buffered in order to remove any minor glitches. When STD bit is set to one (S-BUS or I2CBUS selected), and TRX bit is reset (receiving data), and STOP bit is set (last byte of current communication), the SPI interface does not generate the Acknowledge, according to S-BUS/I2CBUS specifications. PCOSCL, PC1-SDA and PC3-SEN lines are standard drive I/O port pins with open-drain output configuration (maximum voltage that can be applied to these pins is VDD+ 0.3V). S-BUS/I2CBUS Protocol Information The S-BUS is a three-wire bidirectional data-bus with functional features similar to the I2CBUS. In fact the S-BUS includes decoding of Start/Stop conditions and the arbitration procedure in case of multimaster system configuration (the ST6369 SPI allows a single-master only operation). The SDA line, in the I2CBUS represents the AND combination of SDA and SEN lines in the S-BUS. If the SDA and the SEN lines are short-circuit connected, they appear as the SDA line of the I2CBUS. The Start/Stop conditions are detected (by the external peripherals suited to work with S-BUS/I2CBUS) in the following way: by a transition of (1 to 0 - On S-BUS 1 Stop) while thethe SEN line at high Start, 0 to SCL line is level. 2 of the SDA (10 - On I CBUS by a transitionSCL line is linehigh Start, 01Stop) while the at level. Start and Stop condition are always generated by the master (ST6369 SPI can only work as single master). The bus is busy after the start condition and can be considered again free only when a certain time delay is left after the stop condition. In the SBUS configuration the SDA line is only allowed to change during the time SCL line is low. After the start information the SEN line returns to high level and remains unchangedfor all the data transmission time. When the transmission is completed the SDA line is set to high level and, at the same time, the SEN line returns to the low level in order to supply the stop information with a low to high transition, while the SCL line is at high level. On the S-BUS, as on the I2CBUS, each eight bit information (byte) is followed by one acknowledged bit which is a high level put on the SDA line by the transmitter. A peripheral that acknowledges has to pull down the SDA line during the acknowledge clock pulse. An addressed receiver has to generate an acknowledge after the reception of each byte; otherwise the SDA line remains at the high level during the ninth clock pulse time. In this case the master transmitter can generate the Stop condition, via the SEN (or SDA in I2CBUS) line, in order to abort the transfer.
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SERIAL PERIPHERAL INTERFACE (Continued) Start/Stop Acknowledge. The timing specs of the S-BUS protocol require that data on the SDA (only on this line for I2CBUS) and SEN lines be stable during the "high" time of SCL. Two exceptions to this rule are foreseen and they are used to signal the start and stop condition of data transfer. - On S-BUS by a transition of the SEN line (10 Start, 01 Stop) while the SCL line is at high level. - On I2CBUS by a transition of the SDA line (10 Start, 01 Stop) while the SCL line is at high level. Data are transmitted in 8-bit groups; after each group, a ninth bit is interposed, with the purpose of acknowledging the transmitting sequence (the transmit device place a "1" on the bus, the acknowledging receiver a "0"). Interface Protocol. This paragraph deals with the description of data protocol structure. The interface protocol includes: - A start condition - A "slave chip address" byte, transmitted by the master, containing two different information: a. the code identifying the device the master wants to address (this information is present in the first seven bits) b. the direction of transmission on the bus (this information is given in the 8th bit of the byte); "0" means "Write", that is from the master to the slave, while "1" means "Read". The addressed slave must always acknowledge. The sequence from, now on, is different according to the value of R/W bit. 1. R/W = "0" (Write) In all the following bytes the master acts as transmitter; the sequence follows with: a. an optional data byte to address (if needed) the slave location to be written (it can be a word address in a memory or a register address, etc.). b. a "data" byte which will be written at the address given in the previous byte. c. further data bytes. d. a STOP condition A data transfer is always terminated by a stop condition generated from the master. The ST6369 peripheral must finish with a stop condition before another start is given. Figure 44 shows an example of write operation. 2. R/W = "1" (Read) In this case the slave acts as transmitter and, therefore, the transmission direction is changed. In read mode two different conditions can be considered: a. The master reads slave immediately after first byte. In this case after the slave address sent from the master with read condition enabled the master transmitter becomes master receiver and the slave receiver becomes slave transmitter. b. The master reads a specified register or location of the slave. In this case the first sent byte will contain the slave address with write condition enabled, then the second byte will specify the address of the register to be read. At this moment a new start is given together with the slave address in read mode and the procedure will proceed as described in previous point "a".
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SERIAL PERIPHERAL INTERFACE (Continued) Figure 41.Master Transmit to Slave Receiver (Write Mode)
ACKNOWLEDGE FROM SLAVE ACKNOWLEDGE FROM SLAVE MSB S SLAVE ADDRESS 0 A WORD ADDRESS A DATA A P ACKNOWLEDGE FROM SLAVE
START
R/W
STOP
Figure 42.Master Reads Slave Immediately After First Byte (read Mode)
ACKNOWLEDGE FROM SLAVE MSB S SLAVE ADDRESS 1 A DATA A ACKNOWLEDGE FROM MASTER MSB DATA 1 P NO ACKNOWLEDGE FROM MASTER
START
R/W
n BYTES
STOP
Figure 43.Master Reads After Setting Slave Register Address (Write Address, Read Data)
ACKNOWLEDGE FROM SLAVE ACKNOWLEDGE FROM SLAVE
S
SLAVE ADDRESS
0
A
X
WORD ADDRESS
A
P
START
R/W ACKNOWLEDGE FROM SLAVE MSB ACKNOWLEDGE FROM MASTER MSB DATA A DATA 1
STOP NO ACKNOWLEDGE FROM MASTER
S
SLAVE ADDRESS
1
A
P
START
R/W
STOP
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SERIAL PERIPHERAL INTERFACE (Continued) S-BUS/I2CBUS Timing Diagrams The clock of the S-BUS/I2CBUS of the ST6369 SPI (single master only) has a fixed bus clock frequency of 62.5KHz. All the devices connected to the bus must be able to follow transfers with freFigure 44. S-BUS Timing Diagram quencies up to 62.5KHz, either by being able to transmit or receive at that speed or by applying the clock synchronization procedure which will force the master into a wait state and stretch low periods.
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SERIAL PERIPHERAL INTERFACE (Continued) Figure 45. I2C BUS Timing Diagram
2 Note: The third pin, SEN, should be high; it is not used in the I CBUS. Logically SDA is the AND of the S-BUS SDA and SEN.
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SERIAL PERIPHERAL INTERFACE (Continued) Compatibility S-BUS/I2CBUS Using the S-BUS protocol it is possible to implement mixed system including S-BUS/I2CBUS bus peripherals. In order to have the compatibility with the I2CBUS peripherals,the devicesincludingthe S-BUS interface must have their SDA and SEN pins connected together as shown in the following Figure 46 (a and b). It is also possible to use mixed S-BUS/I2CBUS protocols as showed in Figure 46 (c). S-BUS peripherals will only react to S-BUS protocol signals, while I2CBUS peripherals will only react to I2CBUS signals. Multimaster configuration is not possible with the ST6369 SPI (single master only).
Figure 46. S-BUS/I2C BUS Mixed Configurations
(a)
(b)
(c)
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SERIAL PERIPHERAL INTERFACE (Continued) Figure 47.Sofware Bus (Hardware Bus Disabled) Timing Diagram
STD SPI Protocol (Shift Register) This protocol is similar to the I2CBUS with the exception that there is no acknowledge pulse and there are no stop or start bits. The clock cannot be slowed down by the externalperipherals. In this case all three outputs should be high in order not to lock the software I/Os from functioning. SPI Standard Bus Protocol: The standard bus protocol is selected by loading the SPI Control
Register 1 (SCR1 Add. EBH). Bit 0 named I2C must be set at one and bit 1 named STD mut be reset. When the standard bus protocol is selected bit 2 of the SCR1 is meaningless. This bit named STOP bit is used only in I2CBUS or SBUS. However take care thet THE STOP BIT MUST BE RESET WHEN THE STANDARD PROTOCOL IS USED. This bit is set to ZERO after RESET.
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14-BIT PWM D/A CONVERTER The ST6369 PWM D/A CONVERTER (HDA) is composed of a 14-bit counter that allows the conversion of the digital content in an analog voltage, available at the HDA output pin, by using Pulse Width Modification (PWM), and Bit Rate Multiplier (BRM) techniques. The tuning word consists of a 14-bit word contained in the registers HDADATA1 (location 0EEH) and HDADATA2 (location 0EFH). Coarse tuning (PWM) is performed using the seven MSBits, while fine tuning (BRM) is performed using the data in the seven LSBits. With all zeros loaded the output is zero; as the tuning voltage increases from all zeros, the number of pulses in one period increas to 128 with all pulses being the same width. For values larger than 128, the PWM takes over and the number of pulses in one period remains constant at 128, but the width changes. At the other end of the scale, when almost all ones are loaded, the pulses will start to link together and the number of pulses will decrease. When all ones are loaded, the output will be almost 100% high but will have a low pulse (1/16384 of the high pulse). Output Details Inside the on-chip D/A CONVERTER are included the register latches, a reference counter, PWM and BRM control circuitry. In the ST6369 the clock for the 14-bit reference counter is 2MHz derived from the 8MHz system clock. From the circuit point of view, the seven most significant bits control the coarse tuning, while the seven least significant bits control the fine tuning. From the application and software point of view, the 14 bits can be considered as one binary number. As already mentioned the coarse tuning consists of a PWM signal with 128 steps ; we can consider the fine tuning to cover 128 coarse tuning cycles. The addition of pulses is described in the following Table.
Table 11. Fine Tuning Pulse Addition
FIne Tuning (7 LSB) 0000001 0000010 0000100 0001000 0010000 0100000 1000000 N of Pulses added at the following cycles (0...127) 64 32, 96 16, 48, 80, 112 8, 24, ....104, 120 4, 12, ....116, 124 2, 6, .....122, 126 1, 3, .....125, 127
The HDA output pin has a standard drivepush-pull output configuration. HDA Tuning Cell Registers Figure 48. HDA Data Register 1
HDADR1 HDA Data Register 1 (0EEH, Write only) D7 D6 D5 D4 D3 D2 D1 D0
HDA Data Bits (LSB)
D7-D0. These are the 8 least significant HDA data bits. Bit 0 is the LSB. This register is undefined on reset. Figure 49. HDA Data Register 2
HDADR2 HDA Data Register 2 (0EFH, Write only) D7 D6 D5 D4 D3 D2 D1 D0
HDA Data Bits (LSB) Unuse d
D7-D6. These bits are not used. D5-D0. These are the 6 most significant HDA data bits. Bit 5 is the MSB. This register is undefined on reset.
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6-BIT PWM D/A CONVERTERS The D/A macrocell contains up to six PWM D/A outputs (31.25kHz repetition, DA0-DA5) with six bit resolution. Each D/A converter of ST6369 is composed by the following main blocks: - pre-divider - 6-bit counter - data latches and compare circuits The pre-divider uses the clock input frequency (8MHz typical) and its output clocks the 6-bit freerunning counter. The data latched in the six registers (E0H, E1H, E2H, E3H, E6H and E7H) control the six D/A outputs (DA0,1,2, 3, 4 and 5). When all zeros are loaded the relevant output is an high logic level; all 1's correspond to a pulse with a 1/64 duty cycle and almost 100% zero level. The repetition frequency is 31.25KHz and is related to the 8MHz clock frequency. Use of a different oscillator frequency will result in a different repetition frequency. All D/A outputs are opendrain with standard current drive capability and able to withstand up to 12V. Figure 50. DA0-DA5 Data/Control Registers
DA0, DA1, DA2, DA3, DA4, DA5 DA0 to DA5 Data/control Registers (E0H, E1H, E2H, E3H, E6H, E7H Write Only) D7 D6 D5 D4 D3 D2 D1 D0
Data Bit 0 Data Bit 1 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 5 Unused Unused
A/D COMPARATOR A/D INPUT, HSYNC/PC6 RESULT, VSYNC RESULT AND O0, O1 OUTPUTS The A/D macrocell contains an A/D comparator with five levels at intervals of 1V from 1V to 5V. The levels can all be lowered by 0.5V to effectively double the resolution. The A/D used to perform the AFC function (when high threshold is selected) has the following voltage levels: 1,2,3,4 and 5V. Bits 0-2 of AFC result register (E4H address) will provide the result in binary form (less than 1V is 000, greater than 5V is 101). If the application requires a greater resolution, the sensitivity can be doubled by clearing to zero bit 2 of the OUTPUTS control register, address E5H. In this case all levels are shifted lower by 0.5V. If the two results are now added within a software routine then the A/D S-curve can be located within a resolution of 0.5V. The A/D input has high impedance able to withstand up to 13V signals (input level tolerances 200mV absolute and 100mv relative to 5V). Figure 52. A/D Inputs Configuration Diagram
DA0-DA5. These are the 6 bits of the PWM digital to analog converter. Undefined after reset. Figure 51.6-bit PWM D/A Output Configuration
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A/D COMPARATOR (Continued) Figure 53. A/D, HSYNC and VSYNC Result Register
ADRR AD Result Register (E4H, Read Only) D7 D6 D5 D4 D3 D2 D1 D0
O0 Data bit O1 Data bit A/D Shift Bit Unuse d
Figure 54. Outputs Control Register
OCR Outputs Control Register (E5H, Write Only) D7 D6 D5 D4 D3 D2 D1 D0
AD2-AD0 A/D = Conv Result HSYNC VSYNC Unused
D7-D5. These bits are not used. VSYNC. This bit reads the status of the VSYNC pin. It is inverted with respect to the pin. HSYNC. This bit reads the status of the HSYNC latch. If a signal has been latched this bit will be high. AD2-AD0. These bits store the real time conversion of the value present on the AD input pin. Undefined reset value. D7, D6, D5, D4, D3. These bits are not used.
A/D Shift. This bit determines the voltage range of the AFC input. Writing a zero will select the 0.5V to 4.5V range. Writing a one will select the 1.0V to 5.0V range. Undefined after reset. O1,O0. These bits control the output pins O1,O0. They are undefined after reset.
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DEDICATED LATCHES Two latches are available which may generate interrupts to the ST6369 core. The HSYNC latch is set either by the falling or rising edge of the signal on pin PC6(HSYNC). If bit 1 (HSYEDGE) of the latches register (E9H) is high, then the latch will be triggered on the rising edge of the signal at PC6(HSYNC). If bit 1 (HSYEDGE) is low, then the latch will be triggered on the falling edge of the signal at PC6(HSYNC). The HSYNC latch can be reset by setting bit 3 (RESHSYLAT) of the latches register; the bit is set only and a high should be written every time the HSYNC latch needs to be reset. If bit 2 (HSYINTEN) of the latches register (E9H) is high, then the output of the HSYNC latch, HSYNCN, may generate an interrupt (#0). HSYNCN is inverted with respect to the state of the HSYNC latch. If bit 2 (HSYINTEN) is low, then the output of the HSYNC latch, HSYNCN, is forced high. The state of the HSYNC latch may be read from bit 3 (HSYNC) of register E4H; if the HSYNC latch is set, then bit 3 will be high. The PWR latch is set either by the falling or rising edge of the signal on pin PC4(PWRIN). If bit 4 (PWREDGE) of the latches register (E9H) is high, then the latch will be triggered on the rising edge of the signal at PC4(PWRIN). If bit 4 (PWREDGE) is low, then the latch will be triggered on the falling edge of the signal at PC4(PWRIN). The PWR latch can be reset by setting bit 6 (RESPWRLAT) of the latches register; the bit is set only and a high should be written every time the PWR latch needs to be reset. If bit 5 (PWRINTEN) of the latches register (E9H) is high, then the output of the PWR latch, PWRINTN, may generate an interrupt (#4). PWRINTN is inverted with respect to the state of the PWR latch. If bit 5 (PWRINTEN) is low, then the output of the PWR latch, PWRINTN, is forced high.
Figure 55. Dedicated Latches Control Register
DLCR Dedicated Latches Control Register (E9H, Write Only) D7 D6 D5 D4 D3 D2 D1 D0
Unuse d HSYEDGE HSYINTEN RESHSYLAT PWREDGE PWRINTEN RESPWRLAT Unuse d
D0. This bit is not used D7. This bit is not used RESPWRLAT. Resets the PWR latch; this bit is set only. PWRINTEN. This bit enables the PWRINTN signal (#4) from the latch to the ST6369 core. Undefined after reset. PWREDGE. The bit determines the edge which will cause the PWRIN latch to be set. If this bit is high, than the PWRIN latch will be set on the rising edge of the PWRIN signal. Undefined after reset. RESHSYLAT. Resets the HSYNC latch; this bit is set only. HSYINTEN. This bit enables the HSYNCN signal (#0) from the latch to the ST6369 core. Undefined after reset. HSYEDGE. The bit determines the edge which will cause the HSYNC latch to be set. If this bit is high, than the HSYNC latch will be set on the rising edge of the HSYNC signal. Undefined after reset.
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SOFTWARE DESCRIPTION The ST6369 software has been designed to ful l y use the hardware in the most efficient way possibl e whil e keeping byte usage to a minimum; in short to provide byte efficient programming capabil ity. The ST6369 Core has the abil ity to set or cl ear any register or RAM l ocation bit of the Data space with a singl e instruction. Furthermore, the program may branch to a sel ected address depending on the status of any bit of the Data space. The carry bit is stored with the val ue of the bit when the SET or RES instruction is processed. Addressing Modes The ST6369 Core has 9 addressing modes which are described in the fol l owing paragraphs. The ST6369 Core uses three different address spaces: Program space, Data space, and Stack space. Program space contains the instructions which are to be executed, pl us the data for immediate mode instructions. Data space contains the Accumul ator, the X,Y,V and W registers, peripheral andInput/Outputregisters, the RAM l ocations and DataROM l ocations (for storage of tabl es and constants). Stack space contains six 12-bit RAM cel l s used to stack the return addresses for subroutines and interrupts. Immediate. In the immediate addressing mode, the operand of the instruction fol l ows the opcode l ocation. As the operand is a ROM byte, the immediate addressing mode is used to access constants which do not change during program execution (e.g., a constant used to initial ize a l oop counter). Direct. In the direct addressing mode, the address of the byte that is processed by the instruction is stored in the l ocation that fol l ows the opcode. Direct addressing al l ows the user to directl y address the 256 bytes in Data Space memory with a singl e two-byte instruction. Short Direct. The Core can address the four RAM registers X,Y,V,W (l ocations 80H, 81H, 82H, 83H) in the short-direct addressing mode. In this case, the instruction is onl y one byte and the sel ection of the l ocation to be processed is contained in the opcode. Short direct addressing is a subset of the direct addressing mode. (Note that 80H and 81H are al so indirect registers). Extended. In the extended addressing mode, the 12-bit address needed to define the instruction is obtained by concatenating the four l ess significant bits of the opcode with the byte fol l owing the opcode. The instructions (JP, CALL) that use the extended addressing mode are abl e to branch to any address of the 4K bytes Program space. An extended addressing mode instruction is twobyte l ong.
Program Counter Relative. The rel ative addressing mode is onl y used in conditional branch instructions. The instruction is used to perform a test and, if the condition is true, a branch with a span of -15 to +16 l ocations around the address of the rel ative instruction. If the condition is not true, the instruction that fol l ows the rel ative instruction is executed. The rel ative addressing mode instruction is one-byte l ong. The opcode is obtained in adding the three most significant bits that characterize the kind of the test, one bit that determines whether the branch is a forward (when it is 0) or backward (when it is 1) branch and the four l ess significant bits that give the span of the branch (0H to FH) that must be added or subtracted to the address of the rel ative instruction to obtain the address of the branch. Bit Direct. In the bit direct addressing mode, the bit to be set or cl eared is part of the opcode, and the byte fol l owing the opcode points to the address of the byte in which the specified bit must be set or cl eared. Thus, any bit in the 256 l ocations of Data space memory can be set or cl eared. Bit Test & Branch. The bit test and branch addressing mode is a combination of direct addressing and rel ative addressing. The bit test and branch instruction is three-byte l ong. The bit identification and the tested condition are incl uded in the opcode byte. The address of the byte to be tested fol l ows immediatel y the opcode in the Program space. The third byte is the jump displ acement, which is in the range of -126 to +129. This displ acement can be determined using a l abel , which is converted by the assembl er. Indirect. In the indirect addressing mode, the byte processed by the register-indirect instruction is at the address pointed by the content of one of the indirect registers, X or Y (80H,81H). The indirect register is sel ected by the bit 4 of the opcode. A register indirect instruction is one byte l ong. Inherent. In the inherent addressing mode, al l the information necessary to execute the instruction is contained in the opcode. These instructions are one byte l ong.
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SOFTWARE DESCRIPTION (Continued) Instruction Set The ST6369 Core has a set of 40 basic instructions. When these instructions are combined with nine addressing modes, 244 usabl e opcodes can be obtained. They can be divided into six different types:l oad/store, arithmetic/l ogic, conditional branch, control instructions, jump/cal l , bit manipul ation. The fol l owing paragraphs describe the different types. Al l the instructions within a given type are presented in individual tabl es. Table 12. Load & Store Instructions
Instruction Addressing Mode
Load & Store. These instructions use one,two or three bytes in rel ation with the addressing mode. One operand is the Accumul ator for LOAD and the other operand is obtained from data memory using one of the addressing modes. For Load Immediate one operand can be any of the 256 data space bytes whil e the other is al ways immediate data. See Tabl e 12.
Bytes
Cycles Z
Flags C
LD A, X LD A, Y LD A, V LD A, W LD X, A LD Y, A LD V, A LD W, A LD A, rr LD rr, A LD A, (X) LD A, (Y) LD (X), A LD (Y), A
Short Direct Short Direct Short Direct Short Direct Short Direct Short Direct Short Direct Short Direct Direct Direct Indirect Indirect Indirect Indirect 2 2 1 1 1 1
1 1 1 1 1 1 1 1 4 4 4 4 4 4
4 4 4 4 4 4 4 4

* * * * * * * * * * * * * *
LDI A, #N LDI rr, #N
Immediate Immediate
2 3
4 4 *
*
*
Notes: X,Y. Indirect Register Pointers, V & W Short Direct Registers # . Immediate data (stored in ROM memory) rr. Data space register . Affected * . Not Affected
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SOFTWARE DESCRIPTION (Continued) Arithmetic and Logic. These instructions are used to perform the arithmetic cal cul ations and l ogic operations. In AND, ADD, CP, SUB instructions one operand is al ways the accumul ator whil e the other can be either a data space memory Table 13. Arithmetic & Logic Instructions
Instruction ADD A, (X) ADD A, (Y) ADD A, rr ADDI A, #N AND A, (X) AND A, (Y) AND A, rr ANDI A, #N CLR A CLR rr COM A CP A, (X) CP A, (Y) CP A, rr CPI A, #N DEC DEC DEC DEC DEC DEC DEC DEC INC INC INC INC INC INC INC INC X Y V W A rr (X) (Y) Addressing Mode Indirect Indirect Direct Immediate Indirect Indirect Direct Immediate Short Direct Direct Inherent Indirect Indirect Direct Immediate Short Direct Short Direct Short Direct Short Direct Direct Direct Indirect Indirect Short Direct Short Direct Short Direct Short Direct Direct Direct Indirect Indirect Inherent Inherent Indirect Indirect Direct Immediate 3 1 1 1 2 2 1 1 1 1 2 2 1 1 1 1 1 1 2 2 1 1 1 2 1 1 2 2 1 1 2 2 2 Bytes 1 1 2 2
content or an immediate val ue in rel ation with the addressing mode. In CLR, DEC, INC instructions the operand can be any of the 256 data space addresses. In COM, RLC, SLA the operand is al ways the accumul ator. See Tabl e 13.
Cycles 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 *
Flags Z * * * * * * * * * * * * * * * * * C * * * *
X Y V W A rr (X) (Y)
RLC A SLA A SUB A, (X) SUB A, (Y) SUB A, rr SUBI A, #N
Notes: X,Y. Indirect Register Pointers, V & W Short Direct Registers # . Immediate data (stored in ROM memory) rr. Data space register
. Affected * . Not Affected
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SOFTWARE DESCRIPTION (Continued) Conditional Branch. The branch instructions achieve a branch in the program when the sel ected condition is met. See Tabl e 14. Bit Manipulation Instructions. These instructions can handl e any bit in data space memory. One group either sets or cl ears. The other group (see Conditional Branch) performs the bit test branch operations.See Tabl e 15. Table 14. Conditional Branch Instructions
Instruction JRC e JRNC e JRZ e JRNZ e JRR b, rr, ee JRS b, rr, ee Branch If C=1 C=0 Z=1 Z=0 Bit = 0 Bit = 1 Bytes 1 1 1 1 3 3
Control Instructions. The control instructions control the MCU operations during program execution. See Tabl e 16Jump and Call. These two instructions are used to perform l ong (12-bit) jumps or subroutines cal l inside the whol e program space. Refer to Tabl e 17.
Cycles 2 2 2 2 5 5
Flags Z * * * * * * C * * * *
Notes: b. 3-bit address rr. Data space register e. 5 bit signed displacement in the range -15 to +16 ee. 8 bit signed displacement in the range -126 to +129
. Affected * . Not Affected
Table 15. Bit Manipulation Instructions
Instruction SET b,rr RES b,rr
Notes: b. 3-bit address; rr. Data space register;
Addressing Mode Bit Direct Bit Direct
* . Not Affected
Bytes 2 2
Cycles 4 4
Flags Z * * C * *
Table 16. Control Instructions
Instruction NOP RET RETI STOP (1) WAIT Addressing Mode Inherent Inherent Inherent Inherent Inherent Bytes 1 1 1 1 1 Cycles 2 2 2 2 2 Flags Z * * * * C * * * *
Notes: 1. This instruction is deactivated and a WAITis automatically executed instead of a STOP if the hardware activated watchdog function is selected. . Affected * . Not Affected
Table 17. Jump & Call Instructions
Instruction CALL abc JP abc
Notes: abc.12-bit address; * . Not Affected
Addressing Mode Extended Extended
Bytes 2 2
Cycles 4 4
Flags Z * * C * *
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SOFTWARE DESCRIPTION (Continued)
Low 0 0000 Hi 0 00 00 1 00 01 2 00 10 3 0011 4 01 00 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111 2 JRNZ e 1 pcr 2 JRNZ e 1 pcr 2 JRNZ e 1 pcr 4 CALL abc 2 ext 4 CALL abc 2 ext 4 CALL abc 2 ext 2 JRNC e 1 pcr 2 JRNC e 1 pcr 2 JRNC e 1 pcr 5 JRR b0 ,rr,ee 3 bt 5 JRS b0 ,rr,ee 3 bt 5 JRR b4 ,rr,ee 3 bt 2 1 2 1 2 1 JRZ 2 JRC e # e pcr 1 prc JRZ 4 INC 2 JRC e x e pcr 1 sd 1 prc JRZ 2 JRC e # e pcr 1 prc 4 LD a,(x) 1 ind 4 LDI a,n n 2 imm 4 CP a,(x) 1 ind 2 JRNZ e 1 pcr 2 JRNZ e 1 pcr 2 JRNZ e 1 pcr 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 JP abc ext JP abc ext JP abc ext 2 JRNC e 1 pcr 2 JRNC e 1 pcr 2 JRNC e 1 pcr 4 RES b0 ,rr 2 b.d 4 SET b0 ,rr 2 b.d 4 RES b4 ,rr 2 b.d 2 1 2 1 2 1 JRZ e pcr JRZ e pcr JRZ e pcr LDI rr,nn 3 imm 4 DEC x 1 sd 4 COM a 1 inh 4 2 JRC e 1 pcr 2 JRC e 1 pcr 2 JRC e 1 pcr LD a,(y) 1 ind 4 LD a,rr 2 dir 4 CP a,(y) 1 ind 4 1 0001 2 0010 3 0011 4 010 0 5 0101 6 0110 7 0111 8 10 00 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111
Low Hi 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC 4 CPI 2 JRNZ e abc e b4 ,rr,ee e a,x e a,nn e 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm 1 pcr 2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 ADD 2 JRNZ e abc e b2 ,rr,ee e # e a,(x) e 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 1 pcr 2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC 4 ADDI 2 JRNZ e abc e b2 ,rr,ee e y e a,n n e 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm 1 pcr 2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 INC 2 JRNZ e abc e b6 ,rr,ee e # e (x) e 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 1 pcr 2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC 2 JRNZ e abc e b6 ,rr,ee e a,y e # e 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 1 pcr 2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 LD 2 JRNZ e abc e b1 ,rr,ee e # e (x),a e 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 1 pcr 2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC 2 JRNZ e abc e b1 ,rr,ee e v e # e 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 1 pcr 2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 AND 2 JRNZ e abc e b5 ,rr,ee e # e a,(x) e 1 pcr 2 ext 1 pcr 3 2 JRNZ 4 CALL 2 JRNC 5 e 1 pcr 2 abc ext 1 e bt 1 JRS 2 pcr JRZ 4
JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 CP abc e b4 ,rr e x,a e a,rr ext 1 pcr 2 b.d. 1 JP 2 JRNC 4 RES 2 pcr 1 sd 1 pcr 2 dir JRZ 2 RETI 2 JRC 4 ADD e inh 1 pcr 1 a,(y) ind
abc e b2 ,rr e ext 1 pcr 2 b.d 1 pcr 1 JP abc ext JP abc ext JP abc ext JP abc ext JP abc ext JP abc 2 JRNC e 1 pcr 2 JRNC e 1 pcr 2 JRNC e 1 pcr 2 JRNC e 1 pcr 2 JRNC e 1 pcr 2 JRNC e 4 SET b2 ,rr 2 b.d 4 RES b6 ,rr 2 b.d 4 SET b6 ,rr 2 b.d 4 RES b1 ,rr 2 b.d 4 SET b1 ,rr 2 b.d 4 RES b5 ,rr 2 1 2 1 2 1 2 1 2 1 2 JRZ e pcr JRZ e pcr JRZ e pcr JRZ e pcr JRZ e pcr JRZ e 4
DEC 2 JRC 4 ADD y e a,rr 1 sd 1 pcr 2 dir 2 STOP 2 JRC 4 INC e (y) 1 inh 1 pcr 1 ind 4 LD 2 JRC 4 INC y,a e rr 1 sd 1 pcr 2 dir 2 JRC 4 LD # e (y),a 1 pcr 1 ind 4 DEC 2 JRC 4 LD v e rr,a 1 sd 1 pcr 2 dir 4 RLC 2 JRC 4 AND a e a,(y) inh 1 pcr 1 ind LD 2 JRC 4 AND
1 prc 1 ind 1 pcr 2 LD 2 JRC 4 ANDI 2 JRNZ 4
ext 1 pcr 2 b.d 1 JP 2 JRNC 4 SET 2
pcr 1 JRZ 4
b5 ,rr,ee e a,v e a,nn e abc e b5 ,rr e v,a e a,rr pcr 3 bt 1 pcr 1 sd 1 prc 2 imm 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 pcr 2 dir # 2 JRC 4 SUB 2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 e a,(x) e abc e b3 ,rr e ext 1 pcr 2 JP 2 JRNC 4 b.d 1 SET 2 RET 2 JRC 4 SUB e a,(y)
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ e abc e b3 ,rr,ee e 1 pcr 2 ext 1 pcr 3 2 JRNZ 4 CALL 2 JRNC 5 e 1 pcr 2 2 JRNZ e 1 pcr 2 JRNZ e 1 pcr abc ext 1 e bt 1 JRS 2 pcr JRZ 4
1 prc 1 ind 1 pcr 2 INC 2 JRC 4 SUBI 2 JRNZ 4
pcr 1 inh 1 pcr 1 ind JRZ 4 DEC 2 JRC 4 SUB
b3 ,rr,ee e w e a,n n e abc e b3 ,rr e w e a,rr pcr 3 bt 1 pcr 1 sd 1 prc 2 imm 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 pcr 2 dir 5 JRR b7 ,rr,ee 3 bt 5 JRS b7 ,rr,ee 3 bt 2 JRZ e # 1 pcr 2 JRZ 4 LD e a,w 1 pcr 1 sd 2 JRC 4 DEC e (x) 1 prc 1 ind 2 JRC e # 1 prc 2 JRNZ e 1 pcr 2 JRNZ e 1 pcr 4 JP abc 2 ext 4 JP abc 2 ext 2 JRNC e 1 pcr 2 JRNC e 1 pcr 4 RES b7 ,rr 2 b.d 4 SET b7 ,rr 2 b.d JRZ e 1 pcr 2 JRZ e 1 pcr 2 2 WAIT 2 JRC e 1 inh 1 pcr 4 LD 2 JRC w,a e 1 sd 1 pcr 4 DEC (y) 1 ind 4 DEC rr 2 dir
4 CALL abc 2 ext 4 CALL abc 2 ext
2 JRNC e 1 pcr 2 JRNC e 1 pcr
Abbreviations for Addressing Modes: Legend: dir Direct # Indicates Illegal Instructions sd Short Direct e 5 Bit Displacement imm Immediate b 3 Bit Address inh Inherent rr1byte dataspace address ext Extended nn 1 byte immediate data b.d Bit Direct abc 12 bit address bt Bit Test ee 8 bit Displacement pcr Program Counter Relative ind Indirect
Cycles Operand Bytes Addressing Mode
2 JRC e 1 pcr
Mnemonic
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ABSOLUTE MAXIMUM RATINGS This product contains devices to protect the inputs against damage due to high static vol tages, however itis advised to take normal precaution to avoid appl ication of any vol tage higher than maximum rated vol tages. For proper operation it is recommended that VI and VO must be higher than VSS and smal l er than VDD. Rel iabil ity is enhanced if unused inputs are connected to an appropriated l ogic vol tage l evel (VDD or VSS).
Power Considerations. The average chip-junction temperature, Tj, in Cel sius can be obtained from : Tj = TA + PD x RthJA Ambient Temperature. Where :TA = RthJA = Package thermal resistance (junction-to ambient). PD = Pint + Pport. Pint = IDD x VDD (chip internal power). Pport = Port power dissipation (determinated by the user).
Value Unit V
SS
Symbol VDD VI VI VO VO IO IO IVDD IVSS Tj TSTG Supply Voltage
Parameter -0.3 to 7.0 V
Input Voltage (AD IN) Input Voltage (Other Inputs)
- 0.3 to +13
V V V V mA mA
V
SS
- 0.3 to VDD +0.3
Output Voltage (PA4-PA7, PC4-PC7, DA0-DA5) Output Voltage (Other Outputs) Current Drain per Pin Excluding V DD, VSS, PA6, PA7 Current Drain per Pin (PA6, PA7) Total Current into VDD (source) Total Current out of VSS (sink) Junction Temperature Storage Temperature 150 -60 to 150 50 150 V
VSS - 0.3 to +13
SS
- 0.3 to VDD +0.3 10 50 mA mA
C C
Note : Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device . This is a stress rating only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
THERMAL CHARACTERISTIC
Symbol RthJA Parameter Thermal Resistance Test Conditions Min. PSDIP42 67 Value Typ. C/W Max. Unit
RECOMMENDED OPERATING CONDITIONS
Symbol TA VDD fOSC fOSDOSC Parameter Operating Temperature Operating Supply Voltage Oscillator Frequency RUN & WAIT Modes On-screen Display Oscillator Frequency Test Conditions Min. 1 Suffix Version 4.5 5.0 0 6.0 8 V 8.1 8.0 MHz MHz Value Typ. Max. 70 C Unit
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EEPROM INFORMATION The ST63xx EEPROM singl e pol y process has been special l y devel oped to achieve 300.000 Write/Erase cycl es and a 10 years data retention. DC ELECTRICAL CHARACTERISTICS (TA = 0 to +70C unl ess otherwise specified)
Symbol VIL VIH VHYS Parameter Input Low Level Voltage Input High Level Voltage Hysteresis Voltage(1) Test Conditions All I/O Pins All I/O Pins All I/O Pins VDD = 5V DA0-DA5, PB1-PB2, PB4-PB6, PC0-PC7, O0, O1, PA0-PA5 VDD = 4.5V IOL = 1.6mA IOL = 5.0mA PA6-PA7 VDD = 4.5V IOL= 1.6mA IOL= 25mA OSCOUT VDD = 4.5V IOL= 0.4mA HDA Output VDD = 4.5V IOL= 0.5mA IOL= 1.6mA PB1-PB2, PB4-PB6, PA0-PA3, VDD = 4.5V IOH = - 1.6mA OSCOUT, VDD = 4.5V IOH= - 0.4mA HDA Output VDD = 4.5V IOH= - 0.5mA PB1-PB2, PB4-PB6, PA0-PA3, PC0-PC3 VIN= VSS OSCIN VIN= VSS VIN= VDD OSCIN All I/O Input Mode no Pull-up VIN= VDD or VSS 4.1 Value Min. 0.2xV 0.8xVDD 1.0 Typ. Max.
DD
Unit V V V
VOL
Low Level Output Voltage
0.4 1.0
V V
VOL
Low Level Output Voltage
0.4 1.0 0.4
V V V
V OL
Low Level Output Voltage
VOL
Low Level Output Voltage
0.4 1.0 V
V V
VOH
High Level Output Voltage
V OH
High Level Output Voltage
4.1
V
V OH
High Level Output Voltage Input Pull Up Current Input Mode with Pull-up Input Leakage Current Input Pull-down current in Reset Input Leakage Current
4.1
V
IPU IIL IIH IIL IIL IIH
- 100
- 50
- 25
mA
- 10 0.1 100 - 10
-1 1
- 0.1 10
A A
10
A
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ST6369
DC ELECTRICAL CHARACTERISTICS (Continued)
Symbol VDDRAM IIL IIH IIL IIH Parameter RAM Retention Voltage in RESET Input Leakage Current Reset Pin with Pull-up VIN= VSS AD Pin VIH= VDD VIL= VSS VIH= 12.0V DA0-DA5, PA4-PA5, PC0-PC7, O0, O1 VOH = VDD DA0-DA5, PA4-PA7, PC4-PC7, O0, O1 VOH = 12V fOSC= 8MHz, ILoad= 0mA VDD= 6.0V fOSC= 8MHz, ILoad= 0mA VDD= 6V fOSC= Not App, ILoad= 0mA VDD= 6V RESET Pin RESET Pin AD Pin VDD = 5V AD Pin Relative to other levels VDD = 5V 0.3xV 0.8xVDD 200 100 6 3 0.1 Test Conditions Value Min. 1.5 - 50 - 30 - 10 Typ. Max. V A Unit
Input Leakage Current
1 -1 40 10
A
IOH
Output Leakage Current
A
IOH IDD IDD IDD VON VOFF VTA VTR
Output Leakage Current High Voltage Supply Current RUN Mode Supply Current WAIT Mode Supply Current at transition to RESET Reset Trigger Level ON Reset Trigger Level OFF Input Level Absolute Tolerance Input Level Relatice Tolerance (1)
40 16 10 1
A mA mA mA
DD
V V mV
mV
Note: 1. Not 100% Tested
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AC ELECTRICAL CHARACTERISTICS (TA = 0 to +70C, fOSC=8MHz, VDD=4.5 to 6.0V unl ess otherwise specified )
Value Symbol Parameter Test Conditions Min. tWRES tO HL Minimum Pulse Width High to Low Transition Time RESET Pin PA6, PA7 VDD = 5V, CL = 1000pF (2) DA0-DA5, PB1-PB2, PB4-PB6, PC0-PC7, VDD = 5V, CL = 100pF PA0-PA3, PB1-PB2, PB4-PB6, PC0-PC3 VDD = 5V, CL = 100pF 175 125 100 Typ. Max. ns ns Unit
tO HL
High to Low Transition Time
20
ns
tO LH
Low to High Transition Time
20
ns
tOH
Data HOLD Time SPI after clock goes low 2 I CBUS/S-BUS Only D/A Converter Repetition Frequency(1) SIO Baud Rate
(1)
ns
f DA f SIO tWEE Endurance Retention CIN COUT COSCIN, COSCOUT
31.25 62.50 TA = 25C One Byte QA LOT Acceptance Criteria TA = 25C All Inputs Pins All outputs Pins 300.000 10 10 10 5 pF pF 5 >1 million 10
kHz kHz ms cycles years
EEPROM Write Time EEPROM WRITE/ERASE Cycles EEPROM Data Retention (4) Input Capacitance (3) Output Capacitance (3) Oscillator Pins Internal Capacitance(3)
pF
Notes: 1. A clock other than 8 MHz will affect the frequency response of those peripherals (D/A, 62.5kHz and SPI) whose clock is derived from the system clock. 2. The rise and fall times of PORT A have been reduced in order to avoid current spikes while maintaining a high drive capability 3. Not 100% Tested 4. Based on extrapolated data
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PACKAGE MECHANICAL DATA Figure 56. ST6369 40 Pin Plastic Dual-In-Line Package
Dim. Min A A1 B B1 C D D1 E E1 K1 K2 L e1 - - 3.18 2.2 0.51 0.38 0.97 0.2 50.30 -
mm Typ Max 4.8 1.77 0.58 1.52 0.3 Min 0.086 0.010 0.015 0.055 0.008
inches Typ Max 0.189 0.069 0.023 0.065 0.009 20.560 - - 0.641 0.508 - - 4.44 - - 1.25 0.10 Number of Pins - - - - 0.174
52.22 1.980 - - 16.3 12.9 - - -
2.54
N
40
ORDERING INFORMATION The fol l owing chapter deal s with the procedure for transfer the Program/Data ROM codes to SGSTHOMSON. Communication of the ROM Codes. To communicate the contents of Program /Data ROM memories to SGS-THOMSON, the customer has to send: - one fil e in INTEL INTELLEC 8/MDS FORMAT (either as an EPROM or in a MS-DOS 5" diskette) for the PROGRAM Memory - one fil e in INTEL INTELLEC 8/MDS FORMAT (either as an EPROM or in a MS-DOS 5" diskette) for the EEPROM initial content (this fil e is optional )
The program ROM shoul d respect the ROM Memory Map as in Tabl e 18. The ROM code must be generated with ST6 assembl er. Before programming the EPROM, the buffer of the EPROM programmer must be fil l ed with FFH. For shipment to SGS-THOMSON the EPROMs shoul d be pl aced in a conductive IC carrier and packaging careful l y.
Customer EEPROM Initial Contents: Format
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a. The content shoul d be written into an INTEL INTELLEC format fil e. b. In the case of 384 bytes of EEPROM, the starting address is 000H and the end address is 7FH. The order of the pages (64 bytes each) is an in the specification (ie. b7, b1 b0: 001, 010, 011, 101, 110. 111). c. Undefined or don't care bytes shoul d have the content FFH. Listing Generation & Verification. When SGSTHOMSON receives the Codes, they are comTable 18. ROM Memory Map
ROM Page Page 0 Device Address 0000H-007FH 0080H-07FFH 0800H-0F9FH 0FA0H-0FEFH 0FF0H-0FF7H 0FF8H-0FFBH 0FFCH-0FFDH 0FFEH-0FFFH 0000H-000FH 0010H-07FFH 0000H-000FH 0010H-07FFH
pared and a computer l isting is generated from them. This l isting refers extractl y to the mask that wil l be used to produce the microcontrol l er. Then the l isting is returned to the customer that must thoroughl y check, compl ete, sign and return it to SGS-THOMSON. The signed l ist constitutes a part of the contractual agreement for the creation of the customer mask. SGS-THOMSON sal es organization wil l provide detail ed information on contractual points. ST6369 MICROCONTROLLER OPTION LIST
EPROM Address (1) 0000H-007FH 0080H-07FFH 0800H-0F9FH 0FA0H-0FEFH 0FF0H-0FF7H 0FF8H-0FFBH 0FFCH-0FFDH 0FFEH-0FFFH 1000H-100FH 1010H-17FFH 1800H-180FH 1810H-1FFFH
Description Reserved User ROM User ROM Reserved Interrupt Vectors Reserved NMI Vector Reset Vector Reserved User ROM Reserved user ROM
Page 1 "STATIC"
Page 2 PAGE 3
Notes:
1. EPROM addresses are related to the use of ST63E69 emulation devices.
ORDERING INFORMATION TABLE
Sales Type ST6369B1/XX ROM/EEPROM Size 8K/384 Bytes D/A Converter 7 Temperature Range 0 to + 70 C Package PDIP40
Note: "XX" Is the ROM code identifier that is allocated by SGS-THOMSON after receipt of all required options and the related ROM file.
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Customer: Address: Contact: Phone No: Reference:
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Package [ ] (p) Temperature Range [ ] (t) For marking one l ine with 16 characters maximum is possibl e Special Marking [ ] (y/n) Notes: (p) B= Dual in Line Pl astic (t) 1= 0 to 70C (N) Letters, digits, ' Line1 " _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _" (N)
. ', ' - ', ' /
' and spaces onl y
Marking: the defaul t marking is equival ent to the sal es type onl y (part number).
CHECK LIST: ROM CODE EEPROM Code (if Desired) YES [] [] NO [] []
Signature Date
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ST63E69 ST63T69
8-BIT EPROM HCMOS MCUs FOR DIGITAL CONTROLLED MULTI FREQUENCY MONITOR
PRELIMINARY DATA
4.5 to 6V supply operating range 8MHz Maximum Clock Frequency User Program EPROM: 7948 Reserved Test EPROM: 244 Data ROM: user selectable size Data RAM: 256 Data EEPROM: 384 bytes bytes bytes bytes
40-Pin Ceramic Dual in Line Package for EPROM version 40-Pin Plastic Dual in Line Package for OTP version Up to 23 software programmable general purpose Inputs/Outputs, including 2 direct LED driving Outputs Two Timers each including an 8-bit counter with a 7-bit programmable prescaler Digital Watchdog Function Serial Peripheral Interface (SPI) supporting S-BUS/ I2C BUS and standard serial protocols One 14-Bit PWM D/A Converter Six 6-Bit PWM D/A Converters One A/D converter with 0.5V resolution Five interrupt vectors (HSYNC/NMI, Timer 1 & 2, VSYNC, PWR INT.) On-chip clock oscillator These EPROM and OTP versions are fully pin to pin compatible with ST6369 ROM version. The development tool of the ST6369 microcontrollers consists of the ST6369-EMU emulation and development system to be connected via a standard RS232 serial line to an MS-DOS Personal Computer. EPROM programming board ST6369-EPB DEVICE SUMMARY
EPROM DEVICE OTP DEVICE EPROM EEPROM (Bytes) (Bytes) 8K 384 D/A Conv. 7
1
CDIP40W
40 1
PDIP40
(Ordering Information at the end of the datasheet)
ST63E69 ST63T69
February 1993
This is Preliminary information from SGS-THOMSON. Details are subject to change without notice.
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Figure 1. ST63E69, T69 Pin Configuration
DA0 DA1 DA2 DA3 DA4 DA5 PB1 PB2 AD PB4 PB5 PB6 PA0 PA1 PA2 PA3 PA4 PA5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VDD PC0 ( SCL ) PC1 ( SDA ) PC2 PC3 ( SEN ) PC4 ( PWRIN ) PC5 PC6 ( HSYNC ) PC7 HDA RESET OSCOUT OSCIN TEST / VP P VSYNC N.C. N.C. O0 O1 V SS
VR0F1375
ST63E69 ST63T69
GENERAL DESCRIPTION The ST63E69 microcontroller is member of the 8-bit HCMOS ST638x family, a series of devices specially oriented to Digital Controlled Multi Frequency Monitor applications. They are the EPROM/OTP versions of the ST6369 ROM device and are suitable for product prototyping and low volume production. ST6369 is based on a building block approach: a common core is surrounded by a combination of on-chip peripherals (macrocells) available from a standard library. Theseperipheralsare designed with the same Core technology providing full compatibility and short design time. Many ofthese macrocells are specially dedicated to DCMF monitor applications. The macrocells of the ST6369 are: two Timer peripherals each including an 8-bit counter with a 7-bit software programmable prescaler (Timer), a digital hardware activated watchdog function (DHWD), a 14-bit voltage synthesis tuning peripheral, a Serial Peripheral Interface (SPI), six 6-bit PWM D/A converters, an A/D converter with 0.5V resolution, a 14bit PWM D/A converter. In addition the following memory resources are available: program EPROM (8K), data RAM (256 bytes), EEPROM (384 bytes).
PA6 ( HD0 ) 19 PA7 ( HD1 ) 20
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Figure 2. ST63E69, T69 Block Diagram
* Refer To Pin Configuration For Additional Information TEST / VP P
HSYNC/PC6
TEST INTERRUPT Inputs PORT A PORT B PORT C
PA0 PB0
PA7 * PB7 *
VSYNC
USER PROGRAM EPROM 8 kBytes
DATA ROM USER SELECTABLE DATA RAM 256 Bytes DATA EEPROM 384 Bytes
SERIAL PERIPHERAL INTERFACE
PC2,PC4 PC7 * PC0 / SCL PC1 / SDA PC3 / SEN
TIMER 1
TIMER 2
PC
STACK STACK STACK STACK STACK STACK LEVEL 1 LEVEL 2 LEVEL 3 LEVEL 4 LEVEL 5 LEVEL 6
DIGITAL WATCHDOG/TIMER
D / A Outputs
HDA,DA0 DA5 AD
8-BIT CORE
A/D Input
POWER SUPPLY
OSCILLATOR
RESET
VDD
VSS
OSCin
OSCout
RESET
VR 0D1753
Table 1. Device Summary
DEVICE ST63E69 ST63T69 EPROM (Bytes) 8K 8K OTPROM (Bytes) RAM (Bytes) 256 256 EEPROM (Bytes) 384 384 1 A/D 1 1 14-bit 6-bit D/A D/A 1 6 6 TARGET ROM DEVICE ST6369 ST6369
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PIN DESCRIPTION VDD and VSS. Power is supplied to the MCU using these two pins. VDD is power and VSS is the ground connection. OSCIN, OSCOUT. These pins are internally connected to the on-chip oscillator circuit. A quartz crystal or a ceramic resonator can be connected between these two pins in order to allow the correct operation of the MCU with various stability/cost trade-offs. The OSCIN pin is the input pin, the OSCOUT pin is the output pin. RESET. The active low RESET pin is used to start the microcontroller to the beginning of its program. Additionally the quartz crystal oscillator will be disabled when the RESET pin is low to reduce power consumption during reset phase. TEST/VPP. The TEST pin must be held at VSS for normal operation. If this pin is connected to a +12.5V level during the reset phase, The EPROM programming mode is entered. CAUTION: Exceeding 13V on TEST/VPP pin will permanently damaged the device PA0-PA7. These 8 lines are organized as one I/O port (A). Each line may be configured as either an input with or without pull-up resistor or as an output under software control of the data direction register. Pins PA4 to PA7 are configured as open-drain outputs (12V drive). On PA4-PA7 pins the input pull-up option is not available while PA6 and PA7 have additional current driving capability (25mA, VOL:1V). PA0 to PA3 pins are configured as pushpull. PB1-PB2, PB4-PB6. These 5 lines are organized as one I/O port (B). Each line may be configured as either an input with or without internal pull-up resistor or as an output under software control of the data direction register.
PC0-PC7. These 8 lines are organized as one I/O port (C). Each line may be configured as either an input with or without internal pull-up resistor or as an output under software control of the data direction register. Pins PC0 to PC3 are configured as open-drain (5V drive) in output mode while PC4 to PC7 are open-drain with 12V drive and the input pull-up options does not exist on these four pins. PC0, PC1 and PC3 lines when in output mode are "ANDed" with the SPI control signals and are all open-drain. PC0 is connected to the SPI clock signal (SCL), PC1 with the SPI data signal (SDA) while PC3 is connected with SPI enable signal (SEN, used in S-BUS protocol). Pin PC4 and PC6 can also be inputs to software programmable edge sensitive latches which can generate interrupts; PC4 can be connected to Power Interrupt while PC6 can be connected to the HSYNC/NMI interrupt line. DA0-DA5. These pins are the six PWM D/A outputs of the 6-bit on-chip D/A converters. These lines have open-drain outputs with 12V drive. The output repetition rate is 31.25KHz (with 8MHz clock). AD. This is the input of the on-chip 10 levels comparator that can be used to implement the Analog Keyboard function. This pin is an high impedance input able to withstand signals with a peak amplitude up to 12V. VSYNC. This is the Vertical Synchronization pin. This pin is connected to an internal timer interrupt. O0, O1. These two lines are output open-drain pins with 12V drive. HDA. This is the output pin of the on-chip 14-bit PWM D/A Converter. This line is a push-pull output with standard drive.
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Table 2. Pin Summary
Pin Function DA0 to DA5 AD HDA TEST/VPP OSCIN OSCOUT RESET PA0-PA3 PA4-PA5 PA6-PA7 PB1-PB2 PB4-PB6 PC0-PC3 PC4-PC7 O0, O1 VDD, VSS Description Output, Open-Drain, 12V Input, High Impedance, 12V Output, Push-Pull Input, Pull-Down, VPP EPROM Programming Voltage Input Input, Resistive Bias, Schmitt Trigger to Reset Logic Only Output, Push-Pull Input, Pull-up, Schmitt Trigger Input I/O, Push-Pull, Software Input Pull-up, Schmitt Trigger Input I/O, Open-Drain, 12V, No Input Pull-up, Schmitt Trigger Input I/O, Open-Drain, 12V, No Input Pull-up, Schmitt Trigger Input, High Drive I/O, Push-Pull, Software Input Pull-up, Schmitt Trigger Input I/O, Push-Pull, Software Input Pull-up, Schmitt Trigger Input I/O, Open-Drain, 5V , Software Input Pull-up, Schmitt Trigger Input I/O, Open-Drain, 12V, No Input Pull-up, Schmitt Trigger Input Output, Open-Drain, 12V Power Supply Pins
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ST63E69,T69 EPROM/OTP DESCRIPTION. The ST63E69 is the EPROM version of the ST6369 ROM product. It is intended for use during the development of an application, and for pre-production and small volume production. The ST63T69 OTP has the same characteristics. They both include EPROM memory instead of the ROM memory of the ST6369, and so the program and constants of the program can be easily modified by the user with the ST63E69 EPROM programming board from SGS-THOMSON. The Table 3 is a summary of the EPROM/ROM map and its reserved area. From a user point of view (with the following exceptions) the ST63E69,T69 products have exactly the same software and hardware features of the ROM version. An additional mode is used to configure the part for programming of the EPROM, this is set by a +12.5V voltage applied to the TEST/VPP pin. The programming of the ST63E69,T69 is described in the User Manual of the EPROM Programming board. On the ST63E69, all the 7948 bytes of PROGRAM memory are available for the user, as all the EPROM memory can be erased by exposure to UV light. On the ST63T69 (OTP device) a reserved area for test purposes exists, as for the ST6369 ROM device. In order to avoid any discrepancy between program functionality when using the EPROM, OTP and ROM it is recommended not to use these reserved areas, even when using the ST63E69.
THE READER IS ASKED TO REFER TO THE DATASHEET OF THE ST6369 ROM-BASED DEVICE FOR FURTHER DETAILS. EPROM ERASING The EPROM of the windowed package of the ST63E69 may be erased by exposure to Ultra Violet light. The erasure characteristic of the ST63E69 EPROM is such that erasure begins when the memory is exposed to light with wave lengths shorter than approximately 4000A. It should be noted that sunlight and some types of fluorescent lamps have wavelengths in the range3000-4000A. It is thus recommended that the window of the ST63E69 package be covered by an opaque label to prevent unintentional erasure problems when testing the application in such an environment. The recommended erasure procedure of the ST63E69 EPROM is exposure to short wave ultraviolet light which has wavelength 2537A. The integrated dose (i.e. UV intensity x exposure time) for erasure should be a minimum of 15 W-sec/cm2. The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with 12000W/cm2 power rating. The ST63E69 should be placed within 2.5 cm (1 inch) of the lamp tubes during erasure.
Table 3. EPROM/ROM Map
ROM Page PAGE 0 Device Address 0000H-007FH 0080H-07FFH 0800H-0F9FH 0FA0H-0FEFH 0FF0H-0FF7H 0FF8H-0FFBH 0FFCH-0FFDH 0FFEH-0FFFH 0000H-000FH 0010H-07FFH 0000H-000FH 0010H-07FFH Description Reserved User ROM User ROM Reserved Interrupt Vectors Reserved NMI Vector Reset Vector Reserved User ROM Reserved User ROM
PAGE 1 "STATIC"
PAGE 2 PAGE 3
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ABSOLUTE MAXIMUM RATINGS This product contains devices to protect the inputs against damage due to high static voltages, however it is advised to take normal precaution to avoid application of any voltage higher than maximum rated voltages. For proper operation it is recommended that VI and VO must be higher than VSS and smaller than VDD. Reliability is enhanced if unused inputs are connected to an appropriated logic voltage level (VDD or VSS).
Power Considerations. The average chip-junction temperature, Tj, in Celsius can be obtained from : Tj = TA + PD x RthJA Where :TA = Ambient Temperature. RthJA= Package thermal resistance (junction-to ambient). PD = Pint + Pport. Pint = IDD x VDD (chip internal power). Pport = Port power dissipation (determinated by the user).
Value Unit V
SS
Symbol VDD VI VI VO VO VPP IO IO IVDD IVSS Tj TSTG Supply Voltage
Parameter -0.3 to 7.0 V
Input Voltage (AD IN) Input Voltage (Other Inputs)
- 0.3 to +13
V V V V
V
SS
- 0.3 to VDD +0.3
Output Voltage (PA4-PA7, PC4-PC7, DA0-DA5) Output Voltage (Other Outputs) EPROM programming Voltage Current Drain per Pin Excluding VDD, VSS, PA6, PA7 Current Drain per Pin (PA6, PA7) Total Current into VDD (source) Total Current out of VSS (sink) Junction Temperature Storage Temperature 150 -60 to 150 50 150 C V -0.3 to 13.0
VSS - 0.3 to +13
SS
- 0.3 to VDD +0.3 V 10 50 mA mA
mA mA
C
Note : Stresses above those listed as "absolute maximum ratings" may cause permanent damage to the device . This is a stress rating only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol TA VDD VPP fOSC Parameter Operating Temperature Operating Supply Voltage EPROM programming Voltage Oscillator Frequency RUN & WAIT Modes Test Conditions Min. 0 4.5 12.0 5.0 12.5 70 6.0 13.0 8 Value Typ. C V V 8.1 MHz Max. Unit
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THERMAL CHARACTERISTIC
Symbol RthJA Parameter Thermal Resistance Test Conditions Min. PDIP40 67 Value Typ. C/W Max. Unit
EEPROM INFORMATION The ST63xx EEPROM single poly process has been speciallydeveloped to achieve 300.000 Write/Erase cycles and a 10 years data retention. DC ELECTRICAL CHARACTERISTICS (TA = 0 to +70C unless otherwise specified)
Symbol VIL VIH VHYS Parameter Input Low Level Voltage Input High Level Voltage Hysteresis Voltage(1) Test Conditions All I/O Pins All I/O Pins All I/O Pins VDD = 5V DA0-DA5, PB1-PB2, PB3-PB6 PC0-PC7, O0, O1, PA0-PA5 VDD = 4.5V IOL = 1.6mA IOL = 5.0mA PA6-PA7 VDD = 4.5V IOL= 1.6mA IOL= 25mA OSCOUT VDD = 4.5V IOL= 0.4mA HDA Output VDD = 4.5V IOL= 0.5mA IOL= 1.6mA PB1-PB2, PB3-PB6, PA0-PA3 VDD = 4.5V IOH = - 1.6mA OSCOUT, VDD = 4.5V IOH= - 0.4mA HDA Output VDD = 4.5V IOH= - 0.5mA 4.1 Value Min. 0.2xV 0.8xVDD 1.0 Typ. Max.
DD
Unit V V V
VOL
Low Level Output Voltage
0.4 1.0
V V
VOL
Low Level Output Voltage
0.4 1.0 0.4
V V V
V OL
Low Level Output Voltage
VOL
Low Level Output Voltage
0.4 1.0 V
V V
VOH
High Level Output Voltage
V OH
High Level Output Voltage
4.1
V
V OH
High Level Output Voltage
4.1
V
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DC ELECTRICAL CHARACTERISTICS (Continued)
Symbol Parameter Input Pull Up Current Input Mode with Pull-up Input Leakage Current Input Pull-down current in Reset Input Leakage Current RAM Retention Voltage in RESET Input Leakage Current Reset Pin with Pull-up VIN= VSS AD Pin VIH= VDD VIL= VSS VIH= 12.0V DA0-DA5, PA4-PA5, PC0-PC7, O0, O1 VOH = VDD DA0-DA5, PA4-PA7, PC4-PC7, O0, O1 VOH = 12V fOSC= 8MHz, ILoad= 0mA VDD= 6.0V fOSC= 8MHz, ILoad= 0mA VDD= 6V fOSC= Not App, ILoad= 0mA VDD= 6V RESET Pin RESET Pin AD Pin VDD = 5V AD Pin Relative to other levels VDD = 5V 0.3xV 0.8xVDD 200 100 6 3 0.1 Test Conditions PB1-PB2, PB3-PB6, PA0-PA3, PC0-PC3 VIN= VSS OSCIN VIN= VSS VIN= VDD OSCIN All I/O Input Mode no Pull-up VIN= VDD or VSS Value Min. - 100 Typ. - 50 Max. - 25 Unit
IPU IIL IIH IIL IIL IIH VDDRAM IIL IIH IIL IIH
mA
- 10 0.1 100
-1 1
- 0.1 10
A A
- 10 1.5 - 50 - 30
10 V - 10 1
A
A
Input Leakage Current
-1 40 10
A
IOH
Output Leakage Current
A
IOH IDD IDD IDD VON VOFF VTA VTR
Output Leakage Current High Voltage Supply Current RUN Mode Supply Current WAIT Mode Supply Current at transition to RESET Reset Trigger Level ON Reset Trigger Level OFF Input Level Absolute Tolerance Input Level Relatice Tolerance (1)
40 16 10 1
A mA mA mA
DD
V V mV mV
Note: 1. Not 100% Tested
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AC ELECTRICAL CHARACTERISTICS (TA = 0 to +70C, fOSC=8MHz, VDD=4.5 to 6.0V unless otherwise specified )
Value Symbol Parameter Test Conditions Min. tWRES tO HL Minimum Pulse Width High to Low Transition Time RESET Pin PA6, PA7 VDD = 5V, CL = 1000pF (2) DA0-DA5, PB1-PB2, PB4-PB6 PC0-PC7 VDD = 5V, CL = 100pF PB1-PB2 , PB4-PB6, PA0-PA3, PC0-PC3 VDD = 5V, CL = 100pF 125 100 Typ. Max. ns ns Unit
tO HL
High to Low Transition Time
20
ns
tO LH
Low to High Transition Time
20
ns
tOH
Data HOLD Time SPI after clock goes low I2CBUS/S-BUS Only D/A Converter Repetition (1) Frequency SIO Baud Rate(1) EEPROM Write Time EEPROM WRITE/ERASE Cycles EEPROM Data Retention (4) Input Capacitance (3) Output Capacitance (3) Oscillator Pins Internal Capacitance(3) TA = 25C, One Byte QA LOT Acceptance Criteria TA = 25C All Inputs Pins All outputs Pins
175
ns
f DA f SIO tWEE Endurance Retention CIN COUT COSCIN, COSCOUT
31.25 62.50 5 300.000 10 10 10 5 pF pF >1 million 10
kHz kHz ms cycles years
pF
Notes: 1. A clock other than 8 MHz will affect the frequency response of those peripherals (D/A, 62.5kHz and SPI) whose clock is derived from the system clock. 2. The rise and fall times of PORT A have been reduced in order to avoid current spikes while maintaining a high drive capability 3. Not 100% Tested 4. Based on extrapolated data
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ST63E69,ST63T69
ORDERING INFORMATION To ensure compatibility between the EPROM/OTP parts and the corresponding ROM families, the following information is provided. The user should take this information into account when programming the memory of the EPROM parts. Communication of the ROM Codes. To communicate the contents of memories to SGS-THOMSON, the customer has to send: - one file in INTEL INTELLEC 8/MDS FORMAT (either as an EPROM or in a MS-DOS 5" diskette) for the EEPROM initial content (this file is optional) - a filled Option List form as described in the OPTION LIST paragraph. The ROM code must be generated with ST6 assembler. Before programming the EPROM, the buffer of the EPROM programmer must be filled with FFh. For shipment to SGS-THOMSON the EPROMs should be placed in a conductive IC carrier and packaging carefully.
Customer EEPROM Initial Contents: Format a. The content should be written into an INTEL INTELLEC format file. b. In the case of 384 bytes of EEPROM, the starting address is 000h and the end address is 7Fh. The order of the pages (64 bytes each) is an in the specification (ie. b7, b1 b0: 001, 010, 011, 101, 110. 111). c. Undefined or don't care bytes should have the content FFh. Listing Generation & Verification. When SGSTHOMSON receives the Codes, they are compared and a computer listing is generated from them. This listing refers extractly to the mask that will be used to produce the microcontroller. Then the listing is returned to the customer that must thoroughly check, complete, sign and return it to SGS-THOMSON. The signed list constitutes a part of the contractual agreement for the creation of the customer mask. SGS-THOMSON sales organization will provide detailed information on contractual points.
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ST63E69,ST63T69
ST63E69, T69 MICROCONTROLLER OPTION LIST
Customer: Address: Contact: Phone No: Reference: Device
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[ ] (d)
Package
[ ] (p)
Temperature Range
[ ] (t)
For marking one line with 16 characters maximum is possible Special Marking [ ] (y/n) Line1 " _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ " (N) (For Plastic Package only) Notes: (d) 1= ST63E69, 2 = ST63T69 (p) B= Plastic Dual in Line, D= Ceramic Dual in line with Window (t) 1= 0 to 70C (N) Letters, digits, ' . ', ' - ', ' / ' and spaces only Marking: the default marking is equivalent to the sales type only (part number).
CHECK LIST: EEPROM Code (if Desired) YES [] NO []
Signature ................................... Date ...........................................
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ST63E69,ST63T69
ORDERING INFORMATION TABLE
Sales Type ST63E69D1/XX ST63T69B1/XX EPROM/EEPROM Size 8K/384 Bytes 8K/384 Bytes D/A Converter 7 7 Temperature Range 0 to + 70 C 0 to + 70 C Package CDIP40W PDIP40
Note: "XX" Is the ROM code identifier that is allocated by SGS-THOMSON after receipt of all required options and the related ROM file.
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of SGS-THOMSON Microelectronics.
(c) 1994 SGS-THOMSON Microelectronics - All rights reserved. Purchase of I C Components by SGS-THOMSON Microelectronics conveys a license under the Philips I C Patent. 2 2 Rights to use these components in an I C system is granted provided that the system conforms to the I C Standard Specification as defined by Philips. SGS-THOMSON Microelectronics Group of Companies Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
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